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authorEddie Hung <eddie@fpgeh.com>2019-08-01 22:21:30 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-07 09:54:27 -0700
commit03ec8d6551f73bdef9112c20e090d24222821c57 (patch)
treec445934e64cd5ca9838fd2b19f098b04b336533e /frontends
parent3090da2d98221435f2d702efee5fa0f5d9fedc68 (diff)
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Run "clean" on mapped_mod in its own design
Diffstat (limited to 'frontends')
-rw-r--r--frontends/aiger/aigerparse.cc32
-rw-r--r--frontends/aiger/aigerparse.h2
2 files changed, 10 insertions, 24 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index bb97c5703..85ee34e2d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -337,7 +337,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
return wire;
}
-void AigerReader::parse_xaiger()
+void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
{
std::string header;
f >> header;
@@ -373,21 +373,6 @@ void AigerReader::parse_xaiger()
if (n0)
module->connect(n0, RTLIL::S0);
- dict<int,IdString> box_lookup;
- for (auto m : design->modules()) {
- auto it = m->attributes.find("\\abc_box_id");
- if (it == m->attributes.end())
- continue;
- if (m->name.begins_with("$paramod"))
- continue;
- auto id = it->second.as_int();
- auto r = box_lookup.insert(std::make_pair(id, m->name));
- if (!r.second)
- log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
- log_id(m), id, log_id(r.first->second));
- log_assert(r.second);
- }
-
// Parse footer (symbol table, comments, etc.)
std::string s;
bool comment_seen = false;
@@ -986,15 +971,16 @@ void AigerReader::post_process()
}
module->fixup_ports();
- design->add(module);
- design->selection_stack.emplace_back(false);
- RTLIL::Selection& sel = design->selection_stack.back();
- sel.select(module);
+ // Insert into a new (temporary) design so that "clean" will only
+ // operate (and run checks on) this one module
+ RTLIL::Design *mapped_design = new RTLIL::Design;
+ mapped_design->add(module);
+ Pass::call(mapped_design, "clean");
+ mapped_design->modules_.erase(module->name);
+ delete mapped_design;
- Pass::call(design, "clean");
-
- design->selection_stack.pop_back();
+ design->add(module);
for (auto cell : module->cells().to_vector()) {
if (cell->type != "$lut") continue;
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index de3c3efbc..583c9d0f9 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -47,7 +47,7 @@ struct AigerReader
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
void parse_aiger();
- void parse_xaiger();
+ void parse_xaiger(const dict<int,IdString> &box_lookup);
void parse_aiger_ascii();
void parse_aiger_binary();
void post_process();