iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	3	-35/+169
*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	1	-1/+1
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07	1	-1/+1
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	6	-13/+63
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	3	-8/+16
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	1	-0/+1
*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10	1	-0/+2
*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	2	-1/+11
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	5	-11/+30
*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07	2	-3/+4
*	Added log_assert() api	Clifford Wolf	2013-05-24	1	-2/+1
*	Fixed memory leak in ilang frontend	Clifford Wolf	2013-05-23	1	-0/+1
*	added option '-Dname[=definition]' to command 'read_verilog'	Johann Glaser	2013-05-19	3	-4/+19
*	Merge branch 'bugfix'	Clifford Wolf	2013-05-16	1	-2/+0
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\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16	1	-2/+0
* \|	Added support for verilog === operator	Clifford Wolf	2013-05-07	1	-0/+2
* \|	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26	1	-6/+4
* \|	Only use sha1 checksums for names of parametric modules when the verbose form...	Clifford Wolf	2013-04-26	1	-9/+20
* \|	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13	1	-4/+4
* \|	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	3	-7/+31
* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	5	-3/+15
* \|	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	3	-6/+30
* \|	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	2	-4/+2
* \|	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	2	-1/+19
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	3	-34/+16
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	4	-11/+28
*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24	1	-1/+3
*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24	2	-5/+35
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	2	-1/+9
*	Added help messages to ilang and verilog frontends	Clifford Wolf	2013-03-01	2	-2/+57
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	4	-4/+4
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	4	-11/+33
*	Added support for "always @(*)"	Clifford Wolf	2013-01-16	1	-0/+3
*	added .gitignore files	Clifford Wolf	2013-01-05	2	-0/+8
*	initial import	Clifford Wolf	2013-01-05	17	-0/+5999