iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	5	-37/+189
*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	2	-1/+11
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07	1	-1/+1
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07	13	-1748/+0
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07	1	-7/+19
*	Fixed handling of $eq and $ne in opt_const	Clifford Wolf	2013-07-07	1	-2/+2
*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05	3	-2/+14
*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05	1	-6/+23
*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05	1	-4/+5
*	Fixed gcc warnings in ezminisat	Clifford Wolf	2013-07-05	1	-2/+2
*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05	1	-0/+13
*	Added xsthammer report generator	Clifford Wolf	2013-07-05	4	-13/+170
*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04	2	-1/+484
*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04	3	-14/+115
*	Documentation updates	Clifford Wolf	2013-07-04	1	-5/+2
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	7	-13/+79
*	Added QMAKE makefile variable	Clifford Wolf	2013-07-03	1	-1/+2
*	Added Altera Quartus support to xsthammer	Clifford Wolf	2013-07-03	3	-2/+39
*	Progress in xsthammer	Clifford Wolf	2013-07-03	5	-9/+23
*	Added vivado support to xsthammer	Clifford Wolf	2013-06-26	5	-7/+69
*	Added SAT support for -all/-max with -verify	Clifford Wolf	2013-06-23	1	-6/+11
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-20	1	-2/+28
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\| *	Added renaming of wires and cells to "rename" command	Clifford Wolf	2013-06-19	1	-2/+28
* \|	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20	6	-8/+120
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*	Added "eval" pass	Clifford Wolf	2013-06-19	6	-189/+316
*	Fixed build with clang	Clifford Wolf	2013-06-18	1	-41/+69
*	Added splitnets command	Clifford Wolf	2013-06-18	2	-0/+110
*	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	Clifford Wolf	2013-06-18	2	-2/+79
*	Added more stuff to xsthammer, found first xst bug	Clifford Wolf	2013-06-17	2	-2/+175
*	Added support for "assign" statements in abc vlparse	Clifford Wolf	2013-06-15	2	-2/+39
*	Added ternary op and concat op to xsthammer	Clifford Wolf	2013-06-15	1	-7/+124
*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14	3	-30/+59
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13	3	-2/+112
*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13	6	-70/+50
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	5	-16/+24
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-12	5	-5/+81
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\| *	Added "scatter" command	Clifford Wolf	2013-06-12	2	-0/+73
\| *	Renamed yosys-show temp files to be dot-files in the users home directory	Clifford Wolf	2013-06-12	1	-3/+3
\| *	Fixed gcc build (c++11 stuff in ezSAT)	Clifford Wolf	2013-06-12	2	-2/+5
* \|	Another fix for a bug found using xsthammer	Clifford Wolf	2013-06-12	2	-4/+18
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*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	7	-138/+227
*	More xsthammer improvements	Clifford Wolf	2013-06-10	2	-21/+27
*	More sign-extension related fixes	Clifford Wolf	2013-06-10	1	-12/+13
*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10	2	-8/+10
*	Progress xsthammer scripts	Clifford Wolf	2013-06-10	3	-27/+37
*	Improvements and fixes in SAT code	Clifford Wolf	2013-06-10	2	-9/+36
*	Added history file read/write to driver	Clifford Wolf	2013-06-10	1	-0/+16
*	Progress in xsthammer: working proof for cell models	Clifford Wolf	2013-06-10	3	-34/+51
*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	2	-1/+11
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	5	-11/+30