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* Enable bison to be customizedFabio Utzig2015-01-081-1/+1
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-021-1/+2
* Improved some warning messagesClifford Wolf2014-12-271-6/+18
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-111-3/+15
* Fixed minor bug in parsing delaysClifford Wolf2014-11-241-1/+4
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-242-3/+7
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-143-6/+14
* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-121-1/+1
* Added log_warning() APIClifford Wolf2014-11-091-6/+6
* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-301-4/+5
* Added support for task and function args in parenthesesClifford Wolf2014-10-271-6/+45
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-232-10/+4
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-161-1/+1
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-151-4/+4
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-151-3/+5
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-153-14/+18
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-112-2/+2
* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-1/+1
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* namespace YosysClifford Wolf2014-09-271-16/+16
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-231-4/+1
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-235-22/+30
* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-221-0/+12
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-212-5/+16
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-212-1/+54
* Added support for global tasks and functionsClifford Wolf2014-08-212-15/+23
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-181-12/+14
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-131-1/+12
* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-071-3/+5
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-061-4/+18
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-051-2/+1
* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-041-1/+7
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-316-3/+24
* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-302-4/+4
* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-291-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-283-5/+2
* Added "make PRETTY=1"Clifford Wolf2014-07-241-3/+3
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-021-0/+7
* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-161-5/+11
* Improved parsing of large integer constantsClifford Wolf2014-06-151-11/+28
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-142-7/+15
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-132-3/+24
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-124-3/+37
* Add support for cell arraysClifford Wolf2014-06-071-0/+7
* made the generate..endgenrate keywords optionalClifford Wolf2014-06-061-4/+8
* added while and repeat support to verilog parserClifford Wolf2014-06-062-1/+29
* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-041-1/+1
* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-201-0/+5
* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-201-1/+1