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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-05 12:15:53 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-05 12:15:53 +0200 |
| commit | 91dd87e60b120119ee34a9961a7b5f33f340282e (patch) | |
| tree | a7e110f443798bc0ef3c070aec0435d3c5e6b02c /frontends/verilog | |
| parent | 0129d41efad623ee95878a673c1c1190261ba3ef (diff) | |
| download | yosys-91dd87e60b120119ee34a9961a7b5f33f340282e.tar.gz yosys-91dd87e60b120119ee34a9961a7b5f33f340282e.tar.bz2 yosys-91dd87e60b120119ee34a9961a7b5f33f340282e.zip | |
Improved scope resolution of local regs in Verilog+AST frontend
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/parser.y | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 1e0168a5f..26e2ddc34 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -599,12 +599,11 @@ wire_name: if (node->is_input || node->is_output) frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str()); } - ast_stack.back()->children.push_back(node); } else { if (node->is_input || node->is_output) node->port_id = current_function_or_task_port_id++; - current_function_or_task->children.push_back(node); } + ast_stack.back()->children.push_back(node); delete $1; }; |