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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-10 16:59:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-10 17:07:24 +0200 |
| commit | 4569a747f8af3880e23408eb93323afc8088b78b (patch) | |
| tree | 81dcea51020173cd4951e8649f8bd8305e7c2591 /frontends/verilog | |
| parent | c7f5aab625bb90e766c1852592fdf42c951716c0 (diff) | |
| download | yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.gz yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.bz2 yosys-4569a747f8af3880e23408eb93323afc8088b78b.zip | |
Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/parser.y | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index a9f69a49c..cf02a56a9 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -142,7 +142,7 @@ input: { ast_stack.push_back(current_ast); } design { ast_stack.pop_back(); - log_assert(SIZE(ast_stack) == 0); + log_assert(GetSize(ast_stack) == 0); for (auto &it : default_attr_list) delete it.second; default_attr_list.clear(); |