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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-07 11:48:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-07 11:48:50 +0200 |
| commit | e275e8eef9ae47670075bd73a671f3acd3c0ca52 (patch) | |
| tree | 415c0b5d2de494ac0d72a92745d3a1c0cc703275 /frontends/verilog | |
| parent | 0b1ce63a19025f73fe4d2a54253134ea9a4de625 (diff) | |
| download | yosys-e275e8eef9ae47670075bd73a671f3acd3c0ca52.tar.gz yosys-e275e8eef9ae47670075bd73a671f3acd3c0ca52.tar.bz2 yosys-e275e8eef9ae47670075bd73a671f3acd3c0ca52.zip | |
Add support for cell arrays
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/parser.y | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 42a8f91c5..f422258c7 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -634,6 +634,13 @@ single_cell: astbuf2->str = *$1; delete $1; ast_stack.back()->children.push_back(astbuf2); + } '(' cell_port_list ')' | + TOK_ID non_opt_range { + astbuf2 = astbuf1->clone(); + if (astbuf2->type != AST_PRIMITIVE) + astbuf2->str = *$1; + delete $1; + ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2)); } '(' cell_port_list ')'; prim_list: |