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* verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
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* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
| | | | | | These are, by the standard, just aliases for wire/wand/wor. Fixes #2918.
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-141-1/+1
| | | | That was added in ecc22f7fedfa639482dbc55a05709da85116a60f
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* sv: support remaining assignment operatorsZachary Snow2021-05-251-4/+11
| | | | | - Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
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* sv: extended support for integer typesZachary Snow2021-02-281-0/+1
| | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-251-1/+1
| | | | | | | | | | Basically: - priority converts to (* full_case *) - unique0 converts to (* parallel_case *) - unique converts to (* parallel_case, full_case *) Fixes #2596.
* Merge pull request #2179 from splhack/static-castclairexen2020-07-011-0/+2
|\ | | | | Support SystemVerilog Static Cast
| * static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+2
| | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-251-0/+2
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Support missing xor-assign operatorLukasz Dalek2020-06-241-0/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Add plus-assignment operatorKamil Rakoczy2020-06-241-0/+1
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Add or-assignment operatorKamil Rakoczy2020-06-241-0/+2
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Merge branch 'master' into structPeter Crozier2020-06-031-7/+8
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| * Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
| |\ | | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
| | * verilog: Move lexer location variables from global namespace to ↵Alberto Gonzalez2020-05-061-6/+5
| | | | | | | | | | | | `VERILOG_FRONTEND` namespace.
| * | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| |/ | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
* | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-2/+4
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* | Implement SV structs.Peter Crozier2020-05-081-1/+6
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* Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-241-1/+1
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* Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-231-2/+15
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* Parser changes to support typedef.Peter2020-03-221-2/+26
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* refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-111-8/+23
| | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace.
* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-19/+53
| | | | and RTLIL nodes.
* verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-1/+1
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* sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-021-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-131-1/+1
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* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-211-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-121-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-021-0/+2
| | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-111-1/+1
| | | | (within always/initial blocks)
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-0/+5
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-0/+5
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+1
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+1
| | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-0/+2
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* | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-0/+2
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| * \ Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-0/+1
| |\ \ | | | | | | | | Add approximate support for SV "var" keyword
| | * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-0/+1
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / Add support for SVA "final" keywordClifford Wolf2019-05-041-0/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add specify parserClifford Wolf2019-04-231-1/+6
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-49/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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