| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix SYNTHESIS always being defined in Verilog frontend | georgerennie | 2020-12-01 | 1 | -0/+3 |
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| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -6/+6 |
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| * | frontend: cleanup to use more ID::*, more dict<> instead of map<> | Eddie Hung | 2020-05-04 | 1 | -1/+1 |
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| * | Merge pull request #1811 from PeterCrozier/typedef_scope | N. Engelhardt | 2020-03-30 | 1 | -1/+2 |
| |\ | | | | | Support module/package/interface/block scope for typedef names. | ||||
| | * | Support module/package/interface/block scope for typedef names. | Peter Crozier | 2020-03-23 | 1 | -1/+2 |
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| * | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 1 | -13/+13 |
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly. | ||||
| * | Build pkg_user_types before parsing in case of changes in the design. | Peter Crozier | 2020-03-22 | 1 | -6/+3 |
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| * | Clear pkg_user_types if no packages following a 'design -reset-vlog'. | Peter | 2020-03-22 | 1 | -0/+4 |
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| * | Parser changes to support typedef. | Peter | 2020-03-22 | 1 | -0/+19 |
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| * | Closes #1717. Add more precise Verilog source location information to AST ↵ | Alberto Gonzalez | 2020-02-23 | 1 | -1/+1 |
| | | | | | and RTLIL nodes. | ||||
| * | Add "verilog_defines -list" and "verilog_defines -reset" | Clifford Wolf | 2019-10-21 | 1 | -0/+16 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -1/+9 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -2/+2 |
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| | * | Include filename in "Executing Verilog-2005 frontend" message, fixes #959 | Clifford Wolf | 2019-04-30 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -5/+13 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -9/+20 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -2/+12 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 1 | -5/+24 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 1 | -1/+22 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 1 | -1/+9 |
| | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -6/+6 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -5/+3 |
| | | | | | Wherever we can report a source-level location. | ||||
| * | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -6/+17 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Bugfix in verilog_defaults argument parser | Clifford Wolf | 2017-12-24 | 1 | -1/+1 |
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| * | Add a paragraph about pre-defined macros to read_verilog help message | Clifford Wolf | 2017-07-21 | 1 | -0/+4 |
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| * | Added "verilog_defines" command | Clifford Wolf | 2016-12-15 | 1 | -0/+60 |
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| * | Bugfix in "read_verilog -D NAME=VAL" handling | Clifford Wolf | 2016-11-28 | 1 | -3/+3 |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -1/+1 |
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| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 1 | -1/+17 |
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| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 1 | -1/+9 |
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| * | No tristate warning message for "read_verilog -lib" | Clifford Wolf | 2016-07-23 | 1 | -3/+3 |
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| * | Small improvements in Verilog front-end docs | Clifford Wolf | 2016-05-20 | 1 | -0/+3 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Fixed typos in verilog_defaults help message | Clifford Wolf | 2016-03-10 | 1 | -3/+3 |
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| * | SystemVerilog also has assume(), added implicit -D FORMAL | Clifford Wolf | 2015-10-13 | 1 | -2/+2 |
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| * | Added read_verilog -nodpi | Clifford Wolf | 2015-09-23 | 1 | -0/+19 |
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| * | Re-created command-reference-manual.tex, copied some doc fixes to online help | Clifford Wolf | 2015-08-14 | 1 | -6/+6 |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
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| * | Add -noautowire option to verilog frontend | Marcus Comstedt | 2015-08-01 | 1 | -1/+8 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | Verilog front-end: define `BLACKBOX in -lib mode | Clifford Wolf | 2015-04-19 | 1 | -1/+2 |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -1/+11 |
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| * | Added "read_verilog -nomeminit" and "nomeminit" attribute | Clifford Wolf | 2015-02-14 | 1 | -1/+15 |
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| * | Print "SystemVerilog" in "read_verilog -sv" log messages | Clifford Wolf | 2014-10-16 | 1 | -1/+1 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -16/+16 |
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| * | Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore | Clifford Wolf | 2014-08-23 | 1 | -4/+1 |
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| * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 1 | -6/+6 |
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| * | Added support for global tasks and functions | Clifford Wolf | 2014-08-21 | 1 | -4/+4 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -0/+3 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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