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* Add merging of "past FFs" to verific importerClifford Wolf2017-07-291-2/+76
* Add minimal support for PSL in VHDL via VerificClifford Wolf2017-07-281-19/+155
* Improve Verific HDL language optionsClifford Wolf2017-07-281-4/+4
* Fix handling of non-user-declared Verific netbusClifford Wolf2017-07-281-2/+3
* Improve Verific SVA importerClifford Wolf2017-07-271-0/+34
* Add log_warning_noprefix() API, Use for Verific warnings and errorsClifford Wolf2017-07-271-1/+1
* Add "verific -import -n" and "verific -import -nosva"Clifford Wolf2017-07-271-14/+36
* Improve Verific SVA import: negedge and $pastClifford Wolf2017-07-271-6/+49
* Improve Verific SVA importerClifford Wolf2017-07-271-37/+58
* Improve Verific bindings (mostly related to SVA)Clifford Wolf2017-07-261-110/+320
* Improve "help verific" messageClifford Wolf2017-07-251-5/+5
* Add "verific -extnets"Clifford Wolf2017-07-251-23/+130
* Improve "verific -all" handlingClifford Wolf2017-07-251-26/+45
* Add "verific -import -d <dump_file"Clifford Wolf2017-07-241-6/+35
* Add "verific -import -flatten" and "verific -import -v"Clifford Wolf2017-07-241-107/+164
* Add "verific -import -k"Clifford Wolf2017-07-221-42/+51
* Improve docs for verific bindings, add simply sby exampleClifford Wolf2017-07-225-48/+89
* Add Verific Release information to logClifford Wolf2017-07-041-0/+12
* Add support for verific mem initializationClifford Wolf2017-02-111-0/+38
* Fix another stupid bug in the same lineClifford Wolf2017-02-111-1/+1
* Add verific support for initialized variablesClifford Wolf2017-02-111-3/+47
* Improve handling of Verific warnings and error messagesClifford Wolf2017-02-111-4/+10
* Fix extremely stupid typoClifford Wolf2017-02-111-1/+1
* Add "rand" and "rand const" verific supportClifford Wolf2017-02-091-0/+41
* Add PSL parser mode to verific front-endClifford Wolf2017-02-081-2/+17
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-2/+2
* Add assert/assume support to verific front-endClifford Wolf2017-02-042-625/+687
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-131-1/+31
* Bugfix in Verific front-endClifford Wolf2016-02-031-2/+5
* Updated verific build instructionsClifford Wolf2016-02-021-2/+0
* Added addBufGate module methodClifford Wolf2016-02-021-0/+5
* Added PRIM_DLATCHRS support to verific front-endClifford Wolf2015-11-241-0/+10
* Fixed performance bug in Verific importerClifford Wolf2015-11-161-10/+12
* Changes for Verific 3.16_484_32_151112Clifford Wolf2015-11-122-3/+6
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-5/+5
* Added read-enable to memory modelClifford Wolf2015-09-251-1/+2
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Verific build fixesClifford Wolf2015-05-172-2/+2
* Added log_warning() APIClifford Wolf2014-11-091-1/+1
* Added "ENABLE_PLUGINS := 0" to verific amd64 build instructionsClifford Wolf2014-11-081-0/+1
* Header changes so it will compile on VSWilliam Speirs2014-10-171-2/+5
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-8/+8
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-062-2/+2
* Added module->uniquify()Clifford Wolf2014-08-161-6/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-3/+3
* Fixed building verific bindingsClifford Wolf2014-08-122-3/+3
* Fixed build of verific bindingsClifford Wolf2014-07-311-11/+11
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-2/+2