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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-11 11:47:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-11 11:47:51 +0100 |
| commit | c449f4b86f66ca4ef2396454f09a73d56ff06512 (patch) | |
| tree | 237346b4570a5fe299f7cd2a0a3904a7e4ee2125 /frontends/verific | |
| parent | fa4a7efe15ccfca6c8200107284d02ee4ddabb9c (diff) | |
| download | yosys-c449f4b86f66ca4ef2396454f09a73d56ff06512.tar.gz yosys-c449f4b86f66ca4ef2396454f09a73d56ff06512.tar.bz2 yosys-c449f4b86f66ca4ef2396454f09a73d56ff06512.zip | |
Fix another stupid bug in the same line
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9af4ce047..cde72a8e3 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -824,7 +824,7 @@ struct VerificImporter SigBit outsig = net_map.at(out); log_assert(outsig.wire && GetSize(outsig.wire) == 1); - outsig.wire->attributes["\\init"] = Const(0, 1); + outsig.wire->attributes["\\init"] = Const(1, 1); module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out)); continue; |