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authorClifford Wolf <clifford@clifford.at>2017-07-28 11:31:27 +0200
committerClifford Wolf <clifford@clifford.at>2017-07-28 11:31:27 +0200
commitacd6cfaf67ac5d8f26bb6cbeead2393ad29b4550 (patch)
tree19dbb1d880d32eb90bf0044921de8110ef35a344 /frontends/verific
parentc1cfca8f54ba75c455580467223b609b72f0f58c (diff)
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Fix handling of non-user-declared Verific netbus
Diffstat (limited to 'frontends/verific')
-rw-r--r--frontends/verific/verific.cc5
1 files changed, 3 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index e56d4531e..1433afefe 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -845,10 +845,11 @@ struct VerificImporter
if (found_new_net)
{
+ RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escape_id(net->Name()) : NEW_ID);
+
if (verbose)
- log(" importing netbus %s.\n", netbus->Name());
+ log(" importing netbus %s as %s.\n", netbus->Name(), log_id(wire_name));
- RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(netbus->Name()));
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
import_attributes(wire->attributes, netbus);