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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-28 15:32:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-28 15:32:54 +0200 |
| commit | 5a828fff34ae8e0da7d887232daa516db1e37a21 (patch) | |
| tree | 3e6b2f64d153d6ba928ad183e5c793742861a06a /frontends/verific | |
| parent | acd6cfaf67ac5d8f26bb6cbeead2393ad29b4550 (diff) | |
| download | yosys-5a828fff34ae8e0da7d887232daa516db1e37a21.tar.gz yosys-5a828fff34ae8e0da7d887232daa516db1e37a21.tar.bz2 yosys-5a828fff34ae8e0da7d887232daa516db1e37a21.zip | |
Improve Verific HDL language options
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1433afefe..7e4e56504 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1473,12 +1473,12 @@ struct VerificPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..\n"); + log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n"); log("\n"); log("Load the specified Verilog/SystemVerilog files into Verific.\n"); log("\n"); log("\n"); - log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdpsl} <vhdl-file>..\n"); + log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl|-vhdpsl} <vhdl-file>..\n"); log("\n"); log("Load the specified VHDL files into Verific.\n"); log("\n"); @@ -1576,7 +1576,7 @@ struct VerificPass : public Pass { return; } - if (GetSize(args) > argidx && args[argidx] == "-sv") { + if (GetSize(args) > argidx && (args[argidx] == "-sv2012" || args[argidx] == "-sv")) { for (argidx++; argidx < GetSize(args); argidx++) if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG)) log_cmd_error("Reading `%s' in SYSTEM_VERILOG mode failed.\n", args[argidx].c_str()); @@ -1607,7 +1607,7 @@ struct VerificPass : public Pass { return; } - if (GetSize(args) > argidx && args[argidx] == "-vhdl2008") { + if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); for (argidx++; argidx < GetSize(args); argidx++) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008)) |