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* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Allow square brackets in liberty identifiersClifford Wolf2018-11-051-1/+2
* Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
* detect ff/latch before processing other nodesargama2018-10-141-0/+17
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Bugfix in liberty parser (as suggested by aiju in #569)Clifford Wolf2018-06-151-1/+1
* Also interpret '&' in liberty functionsSergiusz Bazanski2018-05-121-1/+1
* Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-031-7/+25
* Improve handling of "bus" pins in liberty front-end (some files use bus.pin.d...Clifford Wolf2018-02-151-0/+6
* Some standard cell libraries include a latch with only set/reset.Staf Verhaegen2018-01-031-4/+23
* Added liberty parser support for types within cell declsClifford Wolf2016-09-231-39/+46
* Added support for bus interfaces to "read_liberty -lib"Clifford Wolf2016-09-181-1/+77
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* namespace YosysClifford Wolf2014-09-271-1/+0
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-2/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-11/+11
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-9/+9
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-61/+61
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-2/+2
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-0/+3
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-2/+2
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-3/+3
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-62/+62
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-62/+62
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-55/+14
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-8/+8
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-8/+8
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-211-10/+10
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-5/+5
* Added "inout" ports support to read_libertyClifford Wolf2014-07-161-1/+6
* Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-161-0/+3
* Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-161-2/+2
* new flags -ignore_miss_func and -ignore_miss_dir for read_libertyJohann Glaser2014-05-281-4/+40
* Added ff and latch support to read_libertyClifford Wolf2014-02-151-40/+254
* Bugfix in expression parser of read_libertyClifford Wolf2014-02-151-2/+1
* Added liberty frontendClifford Wolf2014-02-152-0/+362