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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /frontends/liberty | |
parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
download | yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.gz yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.bz2 yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.zip |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'frontends/liberty')
-rw-r--r-- | frontends/liberty/liberty.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 0107b974a..d5f172f03 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -476,7 +476,7 @@ struct LibertyFrontend : public Frontend { std::string cell_name = RTLIL::escape_id(cell->args.at(0)); - if (design->modules.count(cell_name)) { + if (design->modules_.count(cell_name)) { if (flag_ignore_redef) continue; log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name)); @@ -564,7 +564,7 @@ struct LibertyFrontend : public Frontend { } module->fixup_ports(); - design->modules[module->name] = module; + design->modules_[module->name] = module; cell_count++; skip_cell:; } |