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author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
commit | e6d33513a5b809facc6e3e5e75d2248bfa94f82b (patch) | |
tree | bcee5a22fc9ac7dca5b871ce667114e5f15d07d0 /frontends/liberty | |
parent | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (diff) | |
download | yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.gz yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.bz2 yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.zip |
Added module->design and cell->module, wire->module pointers
Diffstat (limited to 'frontends/liberty')
-rw-r--r-- | frontends/liberty/liberty.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index da16ab33f..d3168ab8e 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -477,7 +477,7 @@ struct LibertyFrontend : public Frontend { std::string cell_name = RTLIL::escape_id(cell->args.at(0)); - if (design->modules_.count(cell_name)) { + if (design->has(cell_name)) { if (flag_ignore_redef) continue; log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name)); @@ -565,7 +565,7 @@ struct LibertyFrontend : public Frontend { } module->fixup_ports(); - design->modules_[module->name] = module; + design->add(module); cell_count++; skip_cell:; } |