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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
commitf9946232adf887e5aa4a48c64f88eaa17e424009 (patch)
tree39594b3287c3369752668456c4a6b1735fb66e77 /frontends/liberty
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff)
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Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'frontends/liberty')
-rw-r--r--frontends/liberty/liberty.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index d7068d468..c476de87a 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -45,11 +45,11 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
std::string id = RTLIL::escape_id(std::string(expr, id_len));
- if (!module->wires.count(id))
+ if (!module->wires_.count(id))
log_error("Can't resolve wire name %s.\n", RTLIL::id2cstr(id));
expr += id_len;
- return module->wires.at(id);
+ return module->wires_.at(id);
}
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
@@ -527,7 +527,7 @@ struct LibertyFrontend : public Frontend {
if (flag_lib && dir->value == "internal")
continue;
- RTLIL::Wire *wire = module->wires.at(RTLIL::escape_id(node->args.at(0)));
+ RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0)));
if (dir && dir->value == "inout") {
wire->port_input = true;