| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fix typo, double "of" | Miodrag Milanovic | 2019-07-16 | 1 | -1/+1 |
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 |
| * | Allow square brackets in liberty identifiers | Clifford Wolf | 2018-11-05 | 1 | -1/+2 |
| * | Minor code cleanups in liberty front-end | Clifford Wolf | 2018-10-17 | 1 | -16/+5 |
| * | detect ff/latch before processing other nodes | argama | 2018-10-14 | 1 | -0/+17 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Bugfix in liberty parser (as suggested by aiju in #569) | Clifford Wolf | 2018-06-15 | 1 | -1/+1 |
| * | Also interpret '&' in liberty functions | Sergiusz Bazanski | 2018-05-12 | 1 | -1/+1 |
| * | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -7/+25 |
| * | Improve handling of "bus" pins in liberty front-end (some files use bus.pin.d... | Clifford Wolf | 2018-02-15 | 1 | -0/+6 |
| * | Some standard cell libraries include a latch with only set/reset. | Staf Verhaegen | 2018-01-03 | 1 | -4/+23 |
| * | Added liberty parser support for types within cell decls | Clifford Wolf | 2016-09-23 | 1 | -39/+46 |
| * | Added support for bus interfaces to "read_liberty -lib" | Clifford Wolf | 2016-09-18 | 1 | -1/+77 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -1/+0 |
| * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 1 | -2/+2 |
| * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 1 | -11/+11 |
| * | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -9/+9 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -61/+61 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -0/+3 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -62/+62 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -62/+62 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -55/+14 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -8/+8 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -8/+8 |
| * | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 | 1 | -10/+10 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 1 | -5/+5 |
| * | Added "inout" ports support to read_liberty | Clifford Wolf | 2014-07-16 | 1 | -1/+6 |
| * | Set blackbox attribute in "read_liberty -lib" | Clifford Wolf | 2014-07-16 | 1 | -0/+3 |
| * | Fixed spelling of "direction" in read_liberty messages | Clifford Wolf | 2014-07-16 | 1 | -2/+2 |
| * | new flags -ignore_miss_func and -ignore_miss_dir for read_liberty | Johann Glaser | 2014-05-28 | 1 | -4/+40 |
| * | Added ff and latch support to read_liberty | Clifford Wolf | 2014-02-15 | 1 | -40/+254 |
| * | Bugfix in expression parser of read_liberty | Clifford Wolf | 2014-02-15 | 1 | -2/+1 |
| * | Added liberty frontend | Clifford Wolf | 2014-02-15 | 2 | -0/+362 |
