aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/ast
Commit message (Collapse)AuthorAgeFilesLines
* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-202-18/+30
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1350 from YosysHQ/clifford/fixsby59Clifford Wolf2019-09-051-7/+18
|\ | | | | Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
| * Properly construct $live and $fair cells from "if (...) assume/assert ↵Clifford Wolf2019-09-021-7/+18
| | | | | | | | | | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Remove newlineEddie Hung2019-08-291-1/+0
| |
* | Restore non-deferred code, deferred case to ignore non constant attrEddie Hung2019-08-291-5/+12
| |
* | read_verilog -defer should still populate module attributesEddie Hung2019-08-281-5/+6
|/
* Do not propagate mem2reg attribute through to resultEddie Hung2019-08-221-1/+2
|
* mem2reg to preserve user attributes and srcEddie Hung2019-08-211-0/+4
|
* handle real values when deriving ast modulesJakob Wenzel2019-08-191-1/+4
|
* Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-121-1/+1
| | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-101-1/+1
|
* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-103-14/+14
|\ | | | | Cleanup a few barnacles across codebase
| * substr() -> compare()Eddie Hung2019-08-073-6/+6
| |
| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-7/+7
| |
| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-15/+2
| |\
| * | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
| | |
* | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-1/+1
| |/ |/|
* | Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
|
* genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
|
* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-193-6/+29
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-073-46/+34
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-074-4/+49
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-034-4/+49
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-273-5/+28
|\ \
| * \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
| |\ \ | | | | | | | | Give error instead of asserting for invalid range, fixes #947
| | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
| | | |
| * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-273-4/+26
| |/ / | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
| | |
* | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
| | |
* | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
| | |
* | | fix indentation across filesStefan Biereigel2019-05-233-61/+81
| | |
* | | implementation for assignments workingStefan Biereigel2019-05-233-14/+83
| | |
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-1/+1
|/ /
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-1/+30
|\ \ | | | | | | Add specify parser
| * | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-032-0/+12
| |\ \
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-2/+8
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-062-0/+3
|\ \ \ \ | | |/ / | |/| |
| * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Determine correct signedness and expression width in for loop unrolling, ↵Clifford Wolf2019-04-221-3/+18
| | | | | | fixes #370 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-221-1/+20
|\ | | | | support repeat loops with constant repeat counts outside of constant functions
| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-091-1/+20
| |
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-04 17:42:45 +0000