iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1845 from YosysHQ/eddie/kernel_speedup	Eddie Hung	2020-04-02	1	-33/+39
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\| *	kernel: more pass by const ref, more speedups	Eddie Hung	2020-03-18	1	-33/+39
* \|	Merge pull request #1783 from boqwxp/astcc_cleanup	Eddie Hung	2020-03-30	1	-13/+20
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\| * \|	Add explanatory comment about inefficient wire removal and remove superfluous...	Alberto Gonzalez	2020-03-30	1	-4/+8
\| * \|	Revert over-aggressive change to a more modest cleanup.	Alberto Gonzalez	2020-03-27	1	-2/+3
\| * \|	Clean up pseudo-private member usage in `frontends/ast/ast.cc`.	Alberto Gonzalez	2020-03-19	1	-11/+13
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* /	Simplify was not being called for packages. Broke typedef enums.	Peter Crozier	2020-03-22	1	-5/+8
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*	Merge pull request #1718 from boqwxp/precise_locations	Claire Wolf	2020-03-03	1	-32/+14
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\| *	Closes #1717. Add more precise Verilog source location information to AST and...	Alberto Gonzalez	2020-02-23	1	-32/+14
* \|	ast: quiet down when deriving blackbox modules	Eddie Hung	2020-02-27	1	-11/+19
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*	add attributes for enumerated values in ilang	Jeff Wang	2020-02-17	1	-0/+1
*	partial rebase of PeterCrozier's enum work onto current master	Jeff Wang	2020-01-16	1	-3/+20
*	Use "(id)" instead of "id" for types as temporary hack	Clifford Wolf	2019-10-14	1	-0/+3
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\| *	sv: Switch parser to glr, prep for typedef	David Shah	2019-10-03	1	-0/+3
* \|	Fix for svinterfaces	Eddie Hung	2019-09-30	1	-2/+8
* \|	module->derive() to be lazy and not touch ast if already derived	Eddie Hung	2019-09-30	1	-32/+50
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*	Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #...	Clifford Wolf	2019-09-20	1	-18/+29
*	Remove newline	Eddie Hung	2019-08-29	1	-1/+0
*	Restore non-deferred code, deferred case to ignore non constant attr	Eddie Hung	2019-08-29	1	-5/+12
*	read_verilog -defer should still populate module attributes	Eddie Hung	2019-08-28	1	-5/+6
*	handle real values when deriving ast modules	Jakob Wenzel	2019-08-19	1	-1/+4
*	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...	Eddie Hung	2019-08-12	1	-1/+1
*	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	David Shah	2019-08-10	1	-1/+1
*	Merge pull request #1258 from YosysHQ/eddie/cleanup	Clifford Wolf	2019-08-10	1	-9/+9
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\| *	substr() -> compare()	Eddie Hung	2019-08-07	1	-2/+2
\| *	RTLIL::S{0,1} -> State::S{0,1}	Eddie Hung	2019-08-07	1	-7/+7
* \|	Allow whitebox modules to be overwritten	Eddie Hung	2019-08-07	1	-1/+1
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*	initialize noblackbox and nowb in AstModule::clone	Jakob Wenzel	2019-07-22	1	-0/+2
*	Add "read_verilog -pwires" feature, closes #1106	Clifford Wolf	2019-06-19	1	-2/+6
*	Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...	Clifford Wolf	2019-06-07	1	-0/+1
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\| *	Initial implementation of elaboration system tasks	Udi Finkelstein	2019-05-03	1	-0/+1
* \|	Merge branch 'master' into wandwor	Stefan Biereigel	2019-05-27	1	-1/+16
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\| * \|	Added support for unsized constants, fixes #1022	Miodrag Milanovic	2019-05-27	1	-1/+16
* \| \|	remove leftovers from ast data structures	Stefan Biereigel	2019-05-27	1	-3/+0
* \| \|	fix indentation across files	Stefan Biereigel	2019-05-23	1	-2/+4
* \| \|	implementation for assignments working	Stefan Biereigel	2019-05-23	1	-0/+3
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* \|	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	1	-2/+2
* \|	Allow $specify[23] cells in blackbox modules	Clifford Wolf	2019-04-23	1	-0/+6
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*	Add "noblackbox" attribute	Clifford Wolf	2019-04-21	1	-17/+27
*	New behavior for front-end handling of whiteboxes	Clifford Wolf	2019-04-20	1	-16/+68
*	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	1	-2/+20
*	Improve "read_verilog -dump_vlog[12]" handling of upto ranges	Clifford Wolf	2019-03-21	1	-3/+6
*	Improve read_verilog debug output capabilities	Clifford Wolf	2019-03-21	1	-9/+17
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-2/+2
*	Various indenting fixes in AST front-end (mostly space vs tab issues)	Clifford Wolf	2018-11-04	1	-6/+3
*	Refactor code to avoid code duplication + added comments	Ruben Undheim	2018-10-20	1	-113/+99
*	Support for SystemVerilog interfaces as a port in the top level module + test...	Ruben Undheim	2018-10-20	1	-3/+105
*	Fixed memory leak	Ruben Undheim	2018-10-20	1	-0/+1
*	Documentation improvements etc.	Ruben Undheim	2018-10-13	1	-3/+28
*	Fix build error with clang	Ruben Undheim	2018-10-12	1	-1/+1