| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\
| |
| | |
Install launcher executable when running yosys-smtbmc on Windows.
|
| |
| |
| |
| | |
Signed-off-by: William D. Jones <thor0505@comcast.net>
|
|/
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Mark dff_init.v as expected to fail since it uses "initial value".
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| |
|
|\
| |
| | |
Fix FIRRTL to Verilog process instance subfield assignment.
|
| |
| |
| |
| |
| |
| | |
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
|
|/
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
per @cliffordwolf
|
|\ |
|
| | |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
|
| |\
| | |
| | | |
write_verilog: correctly emit asynchronous transparent ports
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This commit fixes two related issues:
* For asynchronous ports, clock is no longer added to domain list.
(This would lead to absurd constructs like `always @(posedge 0)`.
* The logic to distinguish synchronous and asynchronous ports is
changed to correctly use or avoid clock in all cases.
Before this commit, the following RTLIL snippet (after memory_collect)
cell $memrd $2
parameter \MEMID "\\mem"
parameter \ABITS 2
parameter \WIDTH 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 1
parameter \TRANSPARENT 1
connect \CLK 1'0
connect \EN 1'1
connect \ADDR \mem_r_addr
connect \DATA \mem_r_data
end
would lead to invalid Verilog:
reg [1:0] _0_;
always @(posedge 1'h0) begin
_0_ <= mem_r_addr;
end
assign mem_r_data = mem[_0_];
Note that there are two potential pitfalls remaining after this
change:
* For asynchronous ports, the \EN input and \TRANSPARENT parameter
are silently ignored. (Per discussion in #760 this is the correct
behavior.)
* For synchronous transparent ports, the \EN input is ignored. This
matches the behavior of the $mem simulation cell. Again, see #760.
|
| | | |
|
| | | |
|
|/ / |
|
|/
|
|
|
|
| |
Smt2Worker::get_id() behavior)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\
| |
| | |
write_verilog: write $tribuf cell as ternary
|
| | |
|
|/ |
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
|
|
|
|
|
|
|
|
| |
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
|
| |
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:
module \\$shift (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (B_SIGNED) begin:BLOCK1
assign Y = $signed(B) < 0 ? A << -B : A >> B;
end else begin:BLOCK2
assign Y = A >> B;
end
endgenerate
endmodule
|
|\
| |
| | |
select: print selection if a -assert-* flag causes an error
|
| | |
|
|\ \
| | |
| | | |
write_verilog: correctly map RTLIL `sync init`
|
| |/ |
|
| |
| |
| |
| | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| |
| |
| |
| | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|/
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|
|
|
| |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\
| |
| | |
improve rlimit handling in smtio.py
|
| |
| |
| |
| | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| |
| |
| |
| | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| |
| |
| |
| | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|/
|
|
|
|
| |
non-incremental solving
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|