iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Refine memory support to deal with general Verilog memory definitions.	Jim Lawson	2019-04-01	1	-30/+173
*	Add support for memory initialization to write_btor	Clifford Wolf	2019-03-23	1	-0/+53
*	Fix BTOR output tags syntax in writye_btor	Clifford Wolf	2019-03-23	1	-2/+1
*	Fix smtbmc.py handling of zero appended steps	Clifford Wolf	2019-03-14	1	-5/+5
*	Fix a syntax bug in ilang backend related to process case statements	Clifford Wolf	2019-03-14	1	-1/+1
*	Merge pull request #869 from cr1901/win-shell	Clifford Wolf	2019-03-14	1	-1/+17
\|\
\| *	Install launcher executable when running yosys-smtbmc on Windows.	William D. Jones	2019-03-13	1	-1/+17
* \|	Improve determinism of IdString DB for similar scripts	Clifford Wolf	2019-03-11	1	-0/+4
\|/
*	Fix signed $shift/$shiftx handling in write_smt2	Clifford Wolf	2019-03-09	1	-1/+2
*	Use SVA label in smt export if available	Clifford Wolf	2019-03-07	1	-2/+2
*	Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails	Jim Lawson	2019-03-04	1	-2/+1
*	Fix "write_edif -gndvccy"	Clifford Wolf	2019-03-01	1	-1/+1
*	Add "write_verilog -siminit"	Clifford Wolf	2019-02-28	1	-2/+11
*	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	1	-3/+3
*	Merge pull request #827 from ucb-bar/firrtlfixes	Clifford Wolf	2019-02-28	1	-8/+20
\|\
\| *	Fix FIRRTL to Verilog process instance subfield assignment.	Jim Lawson	2019-02-25	1	-8/+20
* \|	Fix smt2 code generation for partially initialized memowy words, fixes #831	Clifford Wolf	2019-02-28	1	-4/+11
\|/
*	Instead of INIT param on cells, use initial statement with hier ref as	Eddie Hung	2019-02-17	1	-18/+13
*	Merge https://github.com/YosysHQ/yosys into dff_init	Eddie Hung	2019-02-17	2	-86/+246
\|\
\| *	Removed unused variables, functions.	Jim Lawson	2019-02-15	1	-20/+0
\| *	Update cells supported for verilog to FIRRTL conversion.	Jim Lawson	2019-02-15	1	-48/+225
\| *	Merge pull request #802 from whitequark/write_verilog_async_mem_ports	Clifford Wolf	2019-02-12	1	-38/+41
\| \|\
\| \| *	write_verilog: correctly emit asynchronous transparent ports.	whitequark	2019-01-29	1	-38/+41
* \| \|	Remove check for cell->name[0] == '$'	Eddie Hung	2019-02-06	1	-1/+1
* \| \|	Refactor	Eddie Hung	2019-02-06	1	-21/+5
* \| \|	write_verilog to cope with init attr on q when -noexpr	Eddie Hung	2019-02-06	1	-2/+32
\|/ /
* /	Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...	Clifford Wolf	2019-02-06	1	-1/+1
\|/
*	Merge pull request #800 from whitequark/write_verilog_tribuf	Clifford Wolf	2019-01-27	1	-0/+12
\|\
\| *	write_verilog: write $tribuf cell as ternary.	whitequark	2019-01-27	1	-0/+12
* \|	write_verilog: escape names that match SystemVerilog keywords.	whitequark	2019-01-27	1	-0/+27
\|/
*	Add "write_edif -gndvccy"	Clifford Wolf	2019-01-17	1	-5/+13
*	Fix handling of $shiftx in Verilog back-end	Clifford Wolf	2019-01-15	1	-3/+6
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	4	-7/+7
*	Squelch a little more trailing whitespace	Larry Doolittle	2018-12-29	1	-3/+3
*	Minor style fixes	Clifford Wolf	2018-12-18	2	-1/+1
*	Add btor ops for $mul, $div, $mod and $concat	makaimann	2018-12-17	2	-2/+38
*	write_verilog: handle the $shift cell.	whitequark	2018-12-16	1	-0/+29
*	Merge pull request #736 from whitequark/select_assert_list	Clifford Wolf	2018-12-16	1	-1/+1
\|\
\| *	write_verilog: add a missing newline.	whitequark	2018-12-16	1	-1/+1
* \|	Merge pull request #729 from whitequark/write_verilog_initial	Clifford Wolf	2018-12-16	1	-0/+2
\|\ \
\| * \|	write_verilog: correctly map RTLIL `sync init`.	whitequark	2018-12-07	1	-0/+2
\| \|/
* \|	Add yosys-smtbmc support for btor witness	Clifford Wolf	2018-12-10	1	-15/+100
* \|	Add "yosys-smtbmc --btorwit" skeleton	Clifford Wolf	2018-12-08	1	-1/+19
* \|	Fix btor init value handling	Clifford Wolf	2018-12-08	1	-9/+13
\|/
*	Add "write_aiger -I -O -B"	Clifford Wolf	2018-11-12	1	-2/+36
*	Merge pull request #693 from YosysHQ/rlimit	Clifford Wolf	2018-11-07	1	-8/+11
\|\
\| *	Limit stack size to 16 MB on Darwin	Clifford Wolf	2018-11-07	1	-1/+4
\| *	Fix for improved smtio.py rlimit code	Clifford Wolf	2018-11-06	1	-1/+1
\| *	Improve stack rlimit code in smtio.py	Clifford Wolf	2018-11-06	1	-8/+8
* \|	Run solver in non-incremental mode whem smtio.py is configured for non-increm...	Clifford Wolf	2018-11-06	1	-3/+12
\|/