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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-16 15:50:16 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-16 15:50:16 +0100 |
| commit | f481ad4d448611467a43b1a2f55980914cc1a701 (patch) | |
| tree | 46f260e34db488814bff43f3f370a9c39c889d23 /backends | |
| parent | 0c69f1d7770a7afc6c07d3fb0adaa8d5548e4f27 (diff) | |
| parent | 7fe770a441a129c509fd4da04b60ada942a28bc8 (diff) | |
| download | yosys-f481ad4d448611467a43b1a2f55980914cc1a701.tar.gz yosys-f481ad4d448611467a43b1a2f55980914cc1a701.tar.bz2 yosys-f481ad4d448611467a43b1a2f55980914cc1a701.zip | |
Merge pull request #729 from whitequark/write_verilog_initial
write_verilog: correctly map RTLIL `sync init`
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index dde03f920..922b4c44c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo if (sync->type == RTLIL::STa) { f << stringf("%s" "always @* begin\n", indent.c_str()); + } else if (sync->type == RTLIL::STi) { + f << stringf("%s" "initial begin\n", indent.c_str()); } else { f << stringf("%s" "always @(", indent.c_str()); if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1) |