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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-06 14:53:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-06 14:53:40 -0800 |
| commit | 20ca795b87b810063cdcee6e92e3922281f6b092 (patch) | |
| tree | 1ac5196e284409f1b06771b9ef7c6a6608db1843 /backends | |
| parent | c373640a3ac6c2f76f0a8dce4e44236154ca24bc (diff) | |
| download | yosys-20ca795b87b810063cdcee6e92e3922281f6b092.tar.gz yosys-20ca795b87b810063cdcee6e92e3922281f6b092.tar.bz2 yosys-20ca795b87b810063cdcee6e92e3922281f6b092.zip | |
Remove check for cell->name[0] == '$'
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 66a9e70d3..7b3a60e61 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); std::string init; - if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { std::stringstream ss; dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); init = ss.str(); |