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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-11 20:12:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-11 20:12:28 +0100 |
| commit | 20c6a8c9b0abb384517c4cc6f58cd29a90bda6ff (patch) | |
| tree | da5cb7ac07229a9a577177171ec3f1eb77c928c6 /backends | |
| parent | d9bb5f3637634ea214194b612aee4bb0c62d7a5c (diff) | |
| download | yosys-20c6a8c9b0abb384517c4cc6f58cd29a90bda6ff.tar.gz yosys-20c6a8c9b0abb384517c4cc6f58cd29a90bda6ff.tar.bz2 yosys-20c6a8c9b0abb384517c4cc6f58cd29a90bda6ff.zip | |
Improve determinism of IdString DB for similar scripts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6818edb7a..83d83f488 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1673,6 +1673,8 @@ struct VerilogBackend : public Backend { bool blackboxes = false; bool selected = false; + auto_name_map.clear(); + reg_wires.clear(); reg_ct.clear(); reg_ct.insert("$dff"); @@ -1779,6 +1781,8 @@ struct VerilogBackend : public Backend { dump_module(*f, "", it->second); } + auto_name_map.clear(); + reg_wires.clear(); reg_ct.clear(); } } VerilogBackend; |