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* When two boxes connect to each other, need not be a (* keep *)Eddie Hung2019-09-191-6/+1
* Add "write_aiger -L"Clifford Wolf2019-09-181-5/+16
* Fix stupid bug in btor back-endClifford Wolf2019-09-181-1/+1
* backends: smt2: use $(CXX) variable for compilerSean Cross2019-09-081-1/+1
* Recognise built-in types (e.g. $_DFF_*)Eddie Hung2019-08-301-3/+3
* Revert "Revert "Fix omode which inserts an output if none exists (otherwise a...Eddie Hung2019-08-281-7/+8
* Revert "Output "h" extension only if boxes"Eddie Hung2019-08-281-32/+28
* Output "h" extension only if boxesEddie Hung2019-08-211-28/+32
* Revert "Fix omode which inserts an output if none exists (otherwise abc9 brea...Eddie Hung2019-08-211-8/+7
* Fix omode which inserts an output if none exists (otherwise abc9 breaks)Eddie Hung2019-08-201-7/+8
* Revert "Only xaig if GetSize(output_bits) > 0"Eddie Hung2019-08-201-149/+147
* Only xaig if GetSize(output_bits) > 0Eddie Hung2019-08-201-147/+149
* Remove sequential extensionEddie Hung2019-08-201-270/+29
* Do not sigmap!Eddie Hung2019-08-201-2/+2
* Minor refactorEddie Hung2019-08-201-7/+6
* Output i/o/h extensions even if no boxes or flopsEddie Hung2019-08-191-65/+66
* Add (* abc_arrival *) attributeEddie Hung2019-08-191-9/+66
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-191-1/+1
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| * Fix various NDEBUG compiler warnings, closes #1255Clifford Wolf2019-08-131-1/+1
* | Use %dEddie Hung2019-08-191-1/+1
* | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1612-209/+353
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| * | Compute abc_scc_break and move CI/CO outside of each abc9Eddie Hung2019-08-161-42/+0
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| * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-109-33/+33
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| | * substr() -> compare()Eddie Hung2019-08-075-6/+6
| | * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-074-12/+12
| | * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-106/+240
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| | * | Use IdString::begins_with()Eddie Hung2019-08-061-2/+2
| | * | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-061-5/+5
| | * | Use State::S{0,1}Eddie Hung2019-08-063-6/+6
| | * | Make liberal use of IdString.in()Eddie Hung2019-08-062-2/+2
| * | | Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cellClifford Wolf2019-08-101-1/+1
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| | * \ \ Merge branch 'master' into firrtl_err_on_unsupported_cellJim Lawson2019-08-079-116/+287
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| | * | | Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ...Jim Lawson2019-07-241-1/+1
| * | | | Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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| * | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-071-93/+203
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| | * | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...Jim Lawson2019-07-311-93/+203
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| * | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-071-13/+37
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| | * | Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
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| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-066-3/+40
| * | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-1/+1
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| | * | Visual Studio build fixMiodrag Milanovic2019-07-311-1/+1
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| * / Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-6/+6
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| * Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
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| | * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| * | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
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| * smt: handle failure of setrlimit syscallN. Engelhardt2019-07-151-1/+5
| * Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
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| | * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
* | | abc_flop to also get topologically sortedEddie Hung2019-07-101-11/+10
* | | Fix clk_pol for FD*_1Eddie Hung2019-07-101-1/+0
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