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* Use %dEddie Hung2019-08-191-1/+1
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* Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1612-209/+353
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| * Compute abc_scc_break and move CI/CO outside of each abc9Eddie Hung2019-08-161-42/+0
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| * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-109-33/+33
| |\ | | | | | | Cleanup a few barnacles across codebase
| | * substr() -> compare()Eddie Hung2019-08-075-6/+6
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| | * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-074-12/+12
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| | * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-106/+240
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| | * | Use IdString::begins_with()Eddie Hung2019-08-061-2/+2
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| | * | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-061-5/+5
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| | * | Use State::S{0,1}Eddie Hung2019-08-063-6/+6
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| | * | Make liberal use of IdString.in()Eddie Hung2019-08-062-2/+2
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| * | | Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cellClifford Wolf2019-08-101-1/+1
| |\ \ \ | | | | | | | | | | FIRRTL error on unsupported cell
| | * \ \ Merge branch 'master' into firrtl_err_on_unsupported_cellJim Lawson2019-08-079-116/+287
| | |\ \ \ | | | | |/ | | | |/| | | | | | | | | | | # Conflicts: # backends/firrtl/firrtl.cc
| | * | | Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ↵Jim Lawson2019-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | backend.
| * | | | Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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| * | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-071-93/+203
| |\ \ \ | | | | | | | | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
| | * | | Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-311-93/+203
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
| * | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-071-13/+37
| |\ \ \ | | |_|/ | |/| | Improved JSON attr/param encoding
| | * | Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-066-3/+40
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-1/+1
| |\ \ | | | | | | | | Visual Studio build fix
| | * | Visual Studio build fixMiodrag Milanovic2019-07-311-1/+1
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| * / Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-6/+6
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| * Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
| |\ | | | | | | write_verilog: dump zero width constants correctly
| | * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again).
| * | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * smt: handle failure of setrlimit syscallN. Engelhardt2019-07-151-1/+5
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| * Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
| |\ | | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| | * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
* | | abc_flop to also get topologically sortedEddie Hung2019-07-101-11/+10
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* | | Fix clk_pol for FD*_1Eddie Hung2019-07-101-1/+0
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* | | Fix spacingEddie Hung2019-07-101-1/+1
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* | | Change how to specify flops to ABC againEddie Hung2019-07-101-10/+20
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* | | Use split_tokens()Eddie Hung2019-07-101-17/+11
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-103-15/+34
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| * | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-positionClifford Wolf2019-07-091-3/+2
| |\ \ | | | | | | | | write_verilog: fix placement of case attributes
| | * | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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| * | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscoreEddie Hung2019-07-091-4/+6
| |\ \ | | |/ | |/| Rename __builtin_bswap32 -> bswap32
| | * Rename __builtin_bswap32 -> bswap32Eddie Hung2019-07-091-4/+6
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| * | verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
| | | | | | | | | | | | This appears to be an omission.
| * | verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
| | | | | | | | | | | | Attributes are not permitted in that position by Verilog grammar.
| * | Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places.
| * write_xaiger to treat unknown cell connections as keep-sEddie Hung2019-07-021-6/+14
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* | Safe side: all flops have different mergeability classEddie Hung2019-07-021-1/+1
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* | Refactor and cope with new abc_flop formatEddie Hung2019-07-011-16/+38
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-017-102/+204
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| * Add generic __builtin_bswap32 functionEddie Hung2019-06-281-0/+15
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| * Also fix write_aiger for UBEddie Hung2019-06-281-26/+26
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| * Fix more potential for undefined behaviour due to container invalidationEddie Hung2019-06-281-6/+10
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| * Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-42/+40
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