aboutsummaryrefslogtreecommitdiffstats
path: root/backends
Commit message (Expand)AuthorAgeFilesLines
* write_xaiger to support non-bit cell connections, and cope with COs for -OEddie Hung2019-02-161-13/+15
* write_aiger -O to write dummy output as __dummy_o__Eddie Hung2019-02-161-2/+5
* Tidy up write_xaigerEddie Hung2019-02-161-8/+6
* write_aiger() to perform CI/CO post-processing and fix symbolsEddie Hung2019-02-161-7/+17
* Fixes needed for DFF circuitsEddie Hung2019-02-151-4/+3
* write_xaiger to cope with unknown cells by transforming them to CI/COEddie Hung2019-02-151-6/+44
* More cleanupEddie Hung2019-02-141-15/+6
* More cleanup of write_xaigerEddie Hung2019-02-141-73/+1
* Get rid of formal stuff from xaiger backendEddie Hung2019-02-141-58/+0
* Merge remote-tracking branch 'origin/read_aiger' into xaigEddie Hung2019-02-131-1/+1
|\
| * Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
* | Merge https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-131-38/+41
|\ \
| * \ Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
| |\ \
| | * | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
* | | | Add write_xaigerEddie Hung2019-02-112-21/+11
* | | | Copy backends/aiger/aiger.cc to xaiger.ccEddie Hung2019-02-081-0/+788
| |_|/ |/| |
* | | RefactorEddie Hung2019-02-061-21/+5
* | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
|/ /
* / Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...Clifford Wolf2019-02-061-1/+1
|/
* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\
| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
|/
* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-024-7/+7
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-3/+3
* Minor style fixesClifford Wolf2018-12-182-1/+1
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
|\
| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
* | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
|\ \
| * | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
| |/
* | Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
* | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
* | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
|/
* Add "write_aiger -I -O -B"Clifford Wolf2018-11-121-2/+36
* Merge pull request #693 from YosysHQ/rlimitClifford Wolf2018-11-071-8/+11
|\
| * Limit stack size to 16 MB on DarwinClifford Wolf2018-11-071-1/+4
| * Fix for improved smtio.py rlimit codeClifford Wolf2018-11-061-1/+1
| * Improve stack rlimit code in smtio.pyClifford Wolf2018-11-061-8/+8
* | Run solver in non-incremental mode whem smtio.py is configured for non-increm...Clifford Wolf2018-11-061-3/+12
|/
* Use conservative stack size for SMT2 on MacOSArjen Roodselaar2018-11-041-1/+6
* Add proper error message for when smtbmc "append" failsClifford Wolf2018-11-041-2/+10
* Add support for signed $shift/$shiftx in smt2 back-endClifford Wolf2018-11-011-1/+3
* adding offset info to memoriesrafaeltp2018-10-181-1/+1
* adding offset info to memoriesrafaeltp2018-10-181-2/+3
* Merge pull request #663 from aman-goel/masterClifford Wolf2018-10-171-32/+51
|\
| * Minor updateAman Goel2018-10-151-1/+1
| * Update to .smv backendAman Goel2018-10-011-33/+52
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-01 01:12:14 +0000