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| author | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-18 16:22:33 -0700 |
|---|---|---|
| committer | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-18 16:22:33 -0700 |
| commit | c7770d9eeaf9fba0c9d07e7cce020fe89ec71600 (patch) | |
| tree | dfa9fcdc4c2087146bd2deffd951cfd8c6d95178 /backends | |
| parent | 609f46eeb7b23fec2140dcfaaa5f3a8377153f43 (diff) | |
| download | yosys-c7770d9eeaf9fba0c9d07e7cce020fe89ec71600.tar.gz yosys-c7770d9eeaf9fba0c9d07e7cce020fe89ec71600.tar.bz2 yosys-c7770d9eeaf9fba0c9d07e7cce020fe89ec71600.zip | |
adding offset info to memories
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 39683922f..dde03f920 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -388,7 +388,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) void dump_memory(std::ostream &f, std::string indent, RTLIL::Memory *memory) { dump_attributes(f, indent, memory->attributes); - f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), (memory->width-1), id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset); + f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), memory->width-1, id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset); } void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, bool gen_signed = true) |