| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fixed "write_verilog -attr2comment" handling of "*/" in strings | Clifford Wolf | 2015-02-13 | 1 | -2/+4 |
| * | Added EDIF backend support for multi-bit cell ports | Clifford Wolf | 2015-02-01 | 1 | -11/+10 |
| * | Shorter "dump" options | Clifford Wolf | 2015-01-31 | 1 | -4/+4 |
| * | Added ENABLE_NDEBUG makefile options | Clifford Wolf | 2015-01-24 | 2 | -2/+4 |
| * | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 | 2 | -50/+26 |
| * | Cosmetic changes in verilog output format | Clifford Wolf | 2015-01-02 | 1 | -5/+10 |
| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 1 | -0/+2 |
| * | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 | 2 | -42/+42 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
| * | Various fixes and improvements in "write_smt2 -bv" | Clifford Wolf | 2014-12-25 | 3 | -11/+43 |
| * | Various fixes and improvements in write_smt2 | Clifford Wolf | 2014-12-25 | 2 | -32/+88 |
| * | Added support for most BV cell types to write_smt2 | Clifford Wolf | 2014-12-25 | 1 | -14/+221 |
| * | Added "write_smt2 -bv" and other write_smt2 improvements | Clifford Wolf | 2014-12-25 | 1 | -172/+153 |
| * | Added write_smt2 (only gate level logic supported so far) | Clifford Wolf | 2014-12-24 | 2 | -0/+353 |
| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -1/+1 |
| * | Added $dffe support to write_verilog | Clifford Wolf | 2014-12-20 | 1 | -3/+14 |
| * | Fixed another bug in write_blif handling of $lut cells | Clifford Wolf | 2014-12-19 | 1 | -1/+1 |
| * | Fixed writing of $lut cells in BLIF backend | Clifford Wolf | 2014-12-17 | 1 | -7/+7 |
| * | Added "write_blif -undef" and support for special "-" true/false/undef type | Clifford Wolf | 2014-12-14 | 1 | -13/+33 |
| * | Added "write_blif -blackbox" | Clifford Wolf | 2014-12-14 | 1 | -2/+16 |
| * | Added "blif -unbuf" feature | Clifford Wolf | 2014-12-14 | 1 | -0/+19 |
| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -1/+1 |
| * | Fixed generation of temp names in verilog backend | Clifford Wolf | 2014-11-07 | 1 | -4/+5 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 2 | -2/+2 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 8 | -42/+28 |
| * | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor | Ahmed Irfan | 2014-09-22 | 12 | -1284/+1139 |
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| | * | Sorting of object names in ilang backend | Clifford Wolf | 2014-09-19 | 2 | -21/+49 |
| | * | Various bug fixes (related to $macc model testing) | Clifford Wolf | 2014-09-06 | 1 | -1/+2 |
| | * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -1/+1 |
| | * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+0 |
| | * | Using $pos models for $bu0 | Clifford Wolf | 2014-09-03 | 1 | -16/+1 |
| | * | Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::... | Clifford Wolf | 2014-09-01 | 1 | -1/+2 |
| | * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 1 | -4/+4 |
| | * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 9 | -582/+579 |
| | * | Fixed AOI/OAI expr handling in verilog backend | Clifford Wolf | 2014-08-16 | 1 | -4/+4 |
| | * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 | 1 | -4/+40 |
| | * | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 | 1 | -2/+2 |
| | * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 2 | -2/+2 |
| | * | Refactoring of CellType class | Clifford Wolf | 2014-08-14 | 1 | -10/+28 |
| | * | Be more conservative with printing decimal numbers in verilog backend | Clifford Wolf | 2014-08-02 | 1 | -2/+3 |
| | * | Improved verilog output for ordinary $mux cells | Clifford Wolf | 2014-08-02 | 1 | -3/+19 |
| | * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 4 | -5/+5 |
| | * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 4 | -19/+19 |
| | * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 4 | -86/+86 |
| | * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 2 | -4/+8 |
| | * | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ | Clifford Wolf | 2014-07-29 | 2 | -338/+0 |
| | * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -1/+3 |
| | * | Added support for "upto" wires to Verilog front- and back-end | Clifford Wolf | 2014-07-28 | 1 | -9/+22 |
| | * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 1 | -0/+2 |
| | * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 7 | -11/+5 |
