| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Add log_assert to ensure no loops | Eddie Hung | 2019-06-04 | 1 | -1/+15 |
| * | Only toposort builtin and abc types | Eddie Hung | 2019-06-04 | 1 | -6/+9 |
| * | When creating new holes cell, inherit parameters too | Eddie Hung | 2019-06-03 | 1 | -1/+3 |
| * | ABC9 to understand flops | Eddie Hung | 2019-05-31 | 1 | -46/+27 |
| * | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 1 | -8/+79 |
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| | * | Fix abc9 with (* keep *) wires | Eddie Hung | 2019-04-23 | 1 | -6/+14 |
| | * | Revert "Temporarily remove 'r' extension" | Eddie Hung | 2019-04-22 | 1 | -7/+77 |
| * | | Fix issue where keep signal became PI, but also box was adding CI driver | Eddie Hung | 2019-05-30 | 1 | -5/+19 |
| * | | Do not re-sort box_module ports | Eddie Hung | 2019-05-30 | 1 | -4/+6 |
| * | | Carry in/out to be the last input/output for chains to be preserved | Eddie Hung | 2019-05-30 | 1 | -0/+38 |
| * | | Fix abc_test024 | Eddie Hung | 2019-05-29 | 1 | -4/+5 |
| * | | Fix for abc9_test022 | Eddie Hung | 2019-05-28 | 1 | -2/+6 |
| * | | Small improvement | Eddie Hung | 2019-05-28 | 1 | -4/+2 |
| * | | Update from master | Eddie Hung | 2019-05-28 | 1 | -59/+56 |
| * | | Map file to include boxes not CI/CO | Eddie Hung | 2019-05-27 | 1 | -45/+38 |
| * | | Instantiate cell type (from sym file) otherwise 'clean' warnings | Eddie Hung | 2019-05-27 | 1 | -2/+4 |
| * | | Add 'cinput' and 'coutput' to symbols file for boxes | Eddie Hung | 2019-05-27 | 1 | -34/+24 |
| * | | Fix "a" connectivity | Eddie Hung | 2019-05-26 | 1 | -5/+30 |
| * | | Fix padding, remove CIs from undriven_bits before erasing undriven POs | Eddie Hung | 2019-05-26 | 1 | -14/+8 |
| * | | Fix "a" extension | Eddie Hung | 2019-05-26 | 1 | -8/+18 |
| * | | Fix "write_xaiger", and to write each box contents into holes | Eddie Hung | 2019-05-25 | 1 | -39/+62 |
| * | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-25 | 2 | -7/+27 |
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| | * | | Fix handling of offset and upto module ports in write_blif, fixes #1040 | Clifford Wolf | 2019-05-25 | 1 | -6/+20 |
| | * | | Add proper error message for btor recursion_guard | Clifford Wolf | 2019-05-24 | 1 | -1/+7 |
| * | | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -3/+7 |
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| | * | | Fix static shift operands, neg result type, minor formatting | Jim Lawson | 2019-05-21 | 1 | -3/+7 |
| * | | | Pad all boxes so that all input/output connections specified | Eddie Hung | 2019-05-21 | 1 | -22/+67 |
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 3 | -11/+129 |
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| | * | | Merge pull request #991 from kristofferkoch/gcc9-warnings | Clifford Wolf | 2019-05-08 | 1 | -1/+2 |
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| | | * | | Fix all warnings that occurred when compiling with gcc9 | Kristoffer Ellersgaard Koch | 2019-05-08 | 1 | -1/+2 |
| | * | | | Fix handling of partial init attributes in write_verilog, fixes #997 | Clifford Wolf | 2019-05-07 | 1 | -1/+2 |
| | * | | | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 1 | -1/+4 |
| | * | | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -15/+71 |
| | * | | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -25/+62 |
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| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | * | | | Add $specify2/$specify3 support to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+47 |
| | * | | | Add support for $assert/$assume/$cover to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+10 |
| * | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-02 | 1 | -25/+62 |
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| | * | | | Re-indent firrtl.cc:struct memory - no functional change. | Jim Lawson | 2019-05-01 | 1 | -25/+25 |
| | * | | | Fix #938 - Crash occurs in case when use write_firrtl command | Jim Lawson | 2019-05-01 | 1 | -4/+41 |
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| * | | | Remove topo sort no-loop assertion, with test | Eddie Hung | 2019-04-24 | 1 | -13/+0 |
| * | | | Fix abc9 with (* keep *) wires | Eddie Hung | 2019-04-23 | 1 | -6/+14 |
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| * | | Temporarily remove 'r' extension | Eddie Hung | 2019-04-22 | 1 | -77/+7 |
| * | | Allow POs to be PIs in XAIG | Eddie Hung | 2019-04-22 | 1 | -7/+4 |
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -0/+8 |
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| | * | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 |
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 1 | -1/+1 |
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| | * | Merge pull request #943 from YosysHQ/clifford/whitebox | Clifford Wolf | 2019-04-20 | 8 | -12/+12 |
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| | | * | Revert "write_json to not write contents (cells/wires) of whiteboxes" | Eddie Hung | 2019-04-18 | 1 | -59/+56 |
| | | * | write_json to not write contents (cells/wires) of whiteboxes | Eddie Hung | 2019-04-18 | 1 | -56/+59 |
