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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:35:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | 0bf9d0087c43f9db3d56cb2bed17268def21eb67 (patch) | |
| tree | d9186950668b1bbf196a9d0b38ba0aa7954ae505 /backends | |
| parent | aec2475a9d7a2a903d5015840a3320ce2cedf5cd (diff) | |
| download | yosys-0bf9d0087c43f9db3d56cb2bed17268def21eb67.tar.gz yosys-0bf9d0087c43f9db3d56cb2bed17268def21eb67.tar.bz2 yosys-0bf9d0087c43f9db3d56cb2bed17268def21eb67.zip | |
Add support for $assert/$assume/$cover to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 9967482d6..1c65e79b7 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1242,6 +1242,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type.in("$assert", "$assume", "$cover")) + { + f << stringf("%s" "always @* if (", indent.c_str()); + dump_sigspec(f, cell->getPort("\\EN")); + f << stringf(") %s(", cell->type.c_str()+1); + dump_sigspec(f, cell->getPort("\\A")); + f << stringf(");\n"); + return true; + } + // FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_ // FIXME: $sr, $dlatch, $memrd, $memwr, $fsm |