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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-29 15:24:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-29 15:24:09 -0700 |
| commit | 1423384367d4fa31f09c6c7b69c1b89edc3dd066 (patch) | |
| tree | dd232b7b323fa4052df8918f33ab0034d488c826 /backends | |
| parent | ecaa7856e96dad8de5ef162bb1c9c5814de5254f (diff) | |
| download | yosys-1423384367d4fa31f09c6c7b69c1b89edc3dd066.tar.gz yosys-1423384367d4fa31f09c6c7b69c1b89edc3dd066.tar.bz2 yosys-1423384367d4fa31f09c6c7b69c1b89edc3dd066.zip | |
Fix abc_test024
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 2ffd460dd..bf696bfd6 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -152,10 +152,11 @@ struct XAigerWriter undriven_bits.insert(bit); unused_bits.insert(bit); - if (wire->port_input) - input_bits.insert(bit); - else if (keep) + if (wire->port_input || keep) { + if (bit != wirebit) + alias_map[bit] = wirebit; input_bits.insert(wirebit); + } if (wire->port_output || keep) { if (bit != wirebit) @@ -166,7 +167,7 @@ struct XAigerWriter } for (auto bit : input_bits) - undriven_bits.erase(bit); + undriven_bits.erase(sigmap(bit)); for (auto bit : output_bits) if (!bit.wire->port_input) |