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authorEddie Hung <eddie@fpgeh.com>2019-04-22 11:19:52 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-22 11:19:52 -0700
commit4883391b6331e62226c46e797f82a31ef9ef81a3 (patch)
tree3779d9d3c226602b96eb6f72e2c780e02c64df3e /backends
parentd06d4f35c376672ad1042b46bb29d7bd2bfa5243 (diff)
parentbc98a463a433e5b1553b307301e67e641a148d3c (diff)
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Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'backends')
-rw-r--r--backends/verilog/verilog_backend.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 855409d0b..9967482d6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -187,6 +187,10 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
{
if (width < 0)
width = data.bits.size() - offset;
+ if (width == 0) {
+ f << "\"\"";
+ return;
+ }
if (nostr)
goto dump_hex;
if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
@@ -340,6 +344,10 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
{
+ if (GetSize(sig) == 0) {
+ f << "\"\"";
+ return;
+ }
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
} else {