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* Add support for memory initialization to write_btorClifford Wolf2019-03-231-0/+53
* Fix BTOR output tags syntax in writye_btorClifford Wolf2019-03-231-2/+1
* Fix smtbmc.py handling of zero appended stepsClifford Wolf2019-03-141-5/+5
* Fix a syntax bug in ilang backend related to process case statementsClifford Wolf2019-03-141-1/+1
* Merge pull request #869 from cr1901/win-shellClifford Wolf2019-03-141-1/+17
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| * Install launcher executable when running yosys-smtbmc on Windows.William D. Jones2019-03-131-1/+17
* | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+4
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* Fix signed $shift/$shiftx handling in write_smt2Clifford Wolf2019-03-091-1/+2
* Use SVA label in smt export if availableClifford Wolf2019-03-071-2/+2
* Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-2/+1
* Fix "write_edif -gndvccy"Clifford Wolf2019-03-011-1/+1
* Add "write_verilog -siminit"Clifford Wolf2019-02-281-2/+11
* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-281-3/+3
* Merge pull request #827 from ucb-bar/firrtlfixesClifford Wolf2019-02-281-8/+20
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| * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-8/+20
* | Fix smt2 code generation for partially initialized memowy words, fixes #831Clifford Wolf2019-02-281-4/+11
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* Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-172-86/+246
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| * Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
| * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-48/+225
| * Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
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| | * write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
* | | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
* | | RefactorEddie Hung2019-02-061-21/+5
* | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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* / Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...Clifford Wolf2019-02-061-1/+1
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* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
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| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-024-7/+7
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-3/+3
* Minor style fixesClifford Wolf2018-12-182-1/+1
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
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| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
* | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
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| * | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
* | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
* | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
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* Add "write_aiger -I -O -B"Clifford Wolf2018-11-121-2/+36
* Merge pull request #693 from YosysHQ/rlimitClifford Wolf2018-11-071-8/+11
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| * Limit stack size to 16 MB on DarwinClifford Wolf2018-11-071-1/+4
| * Fix for improved smtio.py rlimit codeClifford Wolf2018-11-061-1/+1
| * Improve stack rlimit code in smtio.pyClifford Wolf2018-11-061-8/+8
* | Run solver in non-incremental mode whem smtio.py is configured for non-increm...Clifford Wolf2018-11-061-3/+12
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* Use conservative stack size for SMT2 on MacOSArjen Roodselaar2018-11-041-1/+6
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