iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24	1	-4/+6
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-7/+7
*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21	1	-1/+44
*	Write yosys version to output files	Clifford Wolf	2013-11-03	1	-2/+2
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-1/+1
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	1	-4/+4
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	1	-0/+1
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-28/+1
*	Added -selected option to various backends	Clifford Wolf	2013-09-03	1	-6/+21
*	More explicit integer output in verilog backend	Clifford Wolf	2013-08-22	1	-2/+2
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-6/+18
*	Avoid verilog-2k in verilog backend	Clifford Wolf	2013-03-21	1	-0/+17
*	More support code for $sr cells	Clifford Wolf	2013-03-14	1	-1/+29
*	Fixed a gcc compiler warning [-Wparentheses]	Clifford Wolf	2013-03-03	1	-1/+2
*	Added more help messages	Clifford Wolf	2013-03-01	1	-1/+25
*	initial import	Clifford Wolf	2013-01-05	3	-0/+947