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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
| commit | 7fccad92f76ddeee653d5dfec17868e9766a683a (patch) | |
| tree | c85e80d5652780f3b543e5937f6e7c6a1d191778 /backends/verilog | |
| parent | cd71c70b4f55c89cdcfd6da23ff5f2002cb7d49d (diff) | |
| download | yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.gz yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.bz2 yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.zip | |
Added more help messages
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d79908006..7c7d518dc 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -854,7 +854,31 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) } /* namespace */ struct VerilogBackend : public Backend { - VerilogBackend() : Backend("verilog") { } + VerilogBackend() : Backend("verilog", "write design to verilog file") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_verilog [options] [filename]\n"); + log("\n"); + log("Write the current design to a verilog file.\n"); + log("\n"); + log(" -norename\n"); + log(" without this option all internal object names (the ones with a dollar\n"); + log(" instead of a backslash prefix) are changed to short names in the\n"); + log(" format '_<number>_'.\n"); + log("\n"); + log(" -noattr\n"); + log(" with this option no attributes are included in the output\n"); + log("\n"); + log(" -attr2comment\n"); + log(" with this option attributes are included as comments in the output\n"); + log("\n"); + log(" -noexpr\n"); + log(" without this option all internal cells are converted to verilog\n"); + log(" expressions.\n"); + log("\n"); + } virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing Verilog backend.\n"); |