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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:27:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-24 11:27:30 +0200 |
| commit | e9dede01ca8834ea3c211862a5d6c0119b2b578a (patch) | |
| tree | b4c2d02cefb1dce8976a222b34c7c8f53d7b4a84 /backends/verilog | |
| parent | 23cf23418cd28b98c11a1ed3fb45dbb927f48e65 (diff) | |
| download | yosys-e9dede01ca8834ea3c211862a5d6c0119b2b578a.tar.gz yosys-e9dede01ca8834ea3c211862a5d6c0119b2b578a.tar.bz2 yosys-e9dede01ca8834ea3c211862a5d6c0119b2b578a.zip | |
Fixed handling of boolean attributes (backends)
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 0eee4af40..88a48b584 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -957,7 +957,7 @@ struct VerilogBackend : public Backend { extra_args(f, filename, args, argidx); for (auto it = design->modules.begin(); it != design->modules.end(); it++) { - if ((it->second->attributes.count("\\placeholder") > 0) != placeholders) + if (it->second->get_bool_attribute("\\placeholder") != placeholders) continue; if (selected && !design->selected_whole_module(it->first)) { if (design->selected_module(it->first)) |