| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Add $specify2/$specify3 support to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+47 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for $assert/$assume/$cover to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+10 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -0/+4 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 1 | -2/+11 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 | |
| | | | | | per @cliffordwolf | |||||
| * | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 1 | -38/+41 | |
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| | * | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760. | |||||
| * | | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 | |
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| * | | Refactor | Eddie Hung | 2019-02-06 | 1 | -21/+5 | |
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| * | | write_verilog to cope with init attr on q when -noexpr | Eddie Hung | 2019-02-06 | 1 | -2/+32 | |
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| * | Merge pull request #800 from whitequark/write_verilog_tribuf | Clifford Wolf | 2019-01-27 | 1 | -0/+12 | |
| |\ | | | | | write_verilog: write $tribuf cell as ternary | |||||
| | * | write_verilog: write $tribuf cell as ternary. | whitequark | 2019-01-27 | 1 | -0/+12 | |
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| * | | write_verilog: escape names that match SystemVerilog keywords. | whitequark | 2019-01-27 | 1 | -0/+27 | |
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| * | Fix handling of $shiftx in Verilog back-end | Clifford Wolf | 2019-01-15 | 1 | -3/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | write_verilog: handle the $shift cell. | whitequark | 2018-12-16 | 1 | -0/+29 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule | |||||
| * | Merge pull request #736 from whitequark/select_assert_list | Clifford Wolf | 2018-12-16 | 1 | -1/+1 | |
| |\ | | | | | select: print selection if a -assert-* flag causes an error | |||||
| | * | write_verilog: add a missing newline. | whitequark | 2018-12-16 | 1 | -1/+1 | |
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| * | | write_verilog: correctly map RTLIL `sync init`. | whitequark | 2018-12-07 | 1 | -0/+2 | |
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| * | adding offset info to memories | rafaeltp | 2018-10-18 | 1 | -1/+1 | |
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| * | adding offset info to memories | rafaeltp | 2018-10-18 | 1 | -2/+3 | |
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| * | Fixed typo in "verilog_write" help message | acw1251 | 2018-09-18 | 1 | -3/+3 | |
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| * | Add $lut support to Verilog back-end | Clifford Wolf | 2018-09-06 | 1 | -0/+13 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 | |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | Add $dlatch support to write_verilog | Clifford Wolf | 2018-04-22 | 1 | -0/+38 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add $shiftx support to verilog front-end | Clifford Wolf | 2017-10-07 | 1 | -0/+17 | |
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| * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -16/+13 | |
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| * | Fixed wrong declaration in Verilog backend | dh73 | 2017-10-01 | 1 | -3/+3 | |
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| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵ | dh73 | 2017-10-01 | 1 | -3/+16 | |
| | | | | | M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now | |||||
| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 1 | -4/+6 | |
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| * | Cleanups and fixed in write_verilog regarding reg init | Clifford Wolf | 2016-11-16 | 1 | -15/+61 | |
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| * | Added hex constant support to write_verilog | Clifford Wolf | 2016-11-03 | 1 | -4/+62 | |
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| * | Adde "write_verilog -renameprefix -v" | Clifford Wolf | 2016-11-01 | 1 | -5/+23 | |
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| * | Bugfix in partial mem write handling in verilog back-end | Clifford Wolf | 2016-08-20 | 1 | -42/+26 | |
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| * | Added missing support for mem read enable ports to verilog back-end | Clifford Wolf | 2016-08-18 | 1 | -6/+14 | |
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| * | Fixed upto handling in verilog back-end | Clifford Wolf | 2016-08-15 | 1 | -0/+3 | |
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| * | Added "write_verilog -defparam" | Clifford Wolf | 2016-07-30 | 1 | -2/+21 | |
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| * | Added "write_verilog -nodec -nostr" | Clifford Wolf | 2016-07-30 | 1 | -4/+27 | |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 | |
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| * | Bugfix in write_verilog for RTLIL processes | Clifford Wolf | 2016-03-14 | 1 | -9/+20 | |
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| * | Bugfixes in writing of memories as Verilog | Clifford Wolf | 2015-09-25 | 1 | -7/+8 | |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -2/+2 | |
| | | | | | Smaller this time | |||||
| * | Re-created command-reference-manual.tex, copied some doc fixes to online help | Clifford Wolf | 2015-08-14 | 1 | -3/+3 | |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 | |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -4/+4 | |
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| * | $mem cell in verilog backend : grouped writes by clock | luke whittlesey | 2015-06-08 | 1 | -54/+108 | |
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| * | Bug fix in $mem verilog backend + changed tests/bram flow of make test. | luke whittlesey | 2015-06-04 | 1 | -14/+16 | |
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| * | Some fixes for $mem in verilog back-end | Clifford Wolf | 2015-05-20 | 1 | -19/+23 | |
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index : iCE40/yosys | |
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