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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-29/+29
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-29/+29
* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-201-17/+21
* Added support for $bu0 to verilog backendClifford Wolf2014-07-201-0/+16
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+22
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-6/+8
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-041-1/+1
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-8/+11
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-241-4/+6
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-221-7/+7
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-211-1/+44
* Write yosys version to output filesClifford Wolf2013-11-031-2/+2
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-241-1/+1
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-241-4/+4
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-181-0/+1
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-28/+1
* Added -selected option to various backendsClifford Wolf2013-09-031-6/+21
* More explicit integer output in verilog backendClifford Wolf2013-08-221-2/+2
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-281-6/+18
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-211-0/+17
* More support code for $sr cellsClifford Wolf2013-03-141-1/+29
* Fixed a gcc compiler warning [-Wparentheses]Clifford Wolf2013-03-031-1/+2
* Added more help messagesClifford Wolf2013-03-011-1/+25
* initial importClifford Wolf2013-01-053-0/+947