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* add buffer option to spice backendPepijn de Vos2021-01-131-7/+15
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* kernel: use more ID::*Eddie Hung2020-04-021-1/+1
* Clean up pseudo-private member usage in `backends/spice/spice.cc`.Alberto Gonzalez2020-04-011-13/+9
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-1/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Also escape "=" in spice outputClifford Wolf2016-05-201-1/+1
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed some typosClifford Wolf2016-04-051-1/+1
* Be more conservative with net names in spice outputClifford Wolf2016-03-021-18/+47
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Added log_warning() APIClifford Wolf2014-11-091-1/+1
* namespace YosysClifford Wolf2014-09-271-0/+4
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-26/+26
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-2/+2
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-4/+4
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-2/+2
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-1/+1
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-4/+4
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-4/+4
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-9/+7
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-11/+11
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-11/+11
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-241-0/+5
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-221-2/+2
* Silenced a gcc warning in spice backendClifford Wolf2013-11-091-1/+1
* Write yosys version to output filesClifford Wolf2013-11-031-4/+1
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-241-1/+1
* A couple of small fixes in SPICE backendClifford Wolf2013-09-151-6/+18
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-141-3/+0
* Added spice backendClifford Wolf2013-09-142-0/+228