Added RTLIL::Cell::has(portname)

1 files changed, 1 insertions, 1 deletions

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 4bc8710e9..653a9f22d 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -80,7 +80,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 			for (RTLIL::Wire *wire : ports) {
 				log_assert(wire != NULL);
 				RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
-				if (cell->connections().count(wire->name) > 0) {
+				if (cell->has(wire->name)) {
 					sig = sigmap(cell->connections().at(wire->name));
 					sig.extend(wire->width, false);
 				}