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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
| commit | edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 (patch) | |
| tree | 602fc633af5de89d2d6d1bda480159318f4aa91d /backends/spice | |
| parent | 48ca1ff9ef5bba939348ceeec75ad310afd9fcf8 (diff) | |
| download | yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.gz yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.bz2 yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.zip | |
Renamed extend() to extend_xx(), changed most users to extend_u0()
Diffstat (limited to 'backends/spice')
| -rw-r--r-- | backends/spice/spice.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 390822ed3..2c614178b 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -84,7 +84,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); if (cell->hasPort(wire->name)) { sig = sigmap(cell->getPort(wire->name)); - sig.extend(wire->width, false); + sig.extend_u0(wire->width, false); } port_sigs.push_back(sig); } |