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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:14:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:14:02 +0200 |
| commit | 3f4e3ca8ad480c2e73e2072ada77078ffd95e08f (patch) | |
| tree | 3117545be59991dc797086c5d273ed97220c75ef /backends/spice | |
| parent | 97a59851a6c411ccb06162d4b31725bf89262378 (diff) | |
| download | yosys-3f4e3ca8ad480c2e73e2072ada77078ffd95e08f.tar.gz yosys-3f4e3ca8ad480c2e73e2072ada77078ffd95e08f.tar.bz2 yosys-3f4e3ca8ad480c2e73e2072ada77078ffd95e08f.zip | |
More RTLIL::Cell API usage cleanups
Diffstat (limited to 'backends/spice')
| -rw-r--r-- | backends/spice/spice.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 653a9f22d..077368771 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -81,7 +81,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); if (cell->has(wire->name)) { - sig = sigmap(cell->connections().at(wire->name)); + sig = sigmap(cell->get(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); |