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Author
Age
Files
Lines
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Rename ASCII tests
Eddie Hung
2019-02-06
15
-0
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+0
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WIP
Eddie Hung
2019-02-06
3
-0
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+247
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Add tests
Eddie Hung
2019-02-04
16
-8
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+109
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Merge pull request #798 from mmicko/master
Clifford Wolf
2019-01-27
1
-1
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+1
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Fixed Anlogic simulation model
Miodrag Milanovic
2019-01-25
1
-1
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+1
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Merge pull request #800 from whitequark/write_verilog_tribuf
Clifford Wolf
2019-01-27
1
-0
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+12
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write_verilog: write $tribuf cell as ternary.
whitequark
2019-01-27
1
-0
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+12
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Merge branch 'whitequark-write_verilog_keyword'
Clifford Wolf
2019-01-27
5
-69
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+27
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Remove asicworld tests for (unsupported) switch-level modelling
Clifford Wolf
2019-01-27
4
-69
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+0
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write_verilog: escape names that match SystemVerilog keywords.
whitequark
2019-01-27
1
-0
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+27
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Merge pull request #796 from whitequark/proc_clean_typo
David Shah
2019-01-25
1
-1
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+1
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proc_clean: fix critical typo.
whitequark
2019-01-23
1
-1
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+1
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Merge pull request #793 from whitequark/proc_clean_fix_fully_def
Clifford Wolf
2019-01-19
1
-1
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+7
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proc_clean: fix fully def check to consider compare/signal length.
whitequark
2019-01-18
1
-1
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+7
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Cleanups in igloo2 example design
Clifford Wolf
2019-01-17
6
-7
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+4
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Add SF2 IO buffer insertion
Clifford Wolf
2019-01-17
6
-3
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+171
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Improve Igloo2 example
Clifford Wolf
2019-01-17
8
-22
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+41
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Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
Clifford Wolf
2019-01-17
1
-2
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+17
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Add "write_edif -gndvccy"
Clifford Wolf
2019-01-17
1
-5
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+13
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Add optional nullstr argument to log_id()
Clifford Wolf
2019-01-15
1
-1
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+3
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Fix handling of $shiftx in Verilog back-end
Clifford Wolf
2019-01-15
1
-3
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+6
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Merge pull request #788 from whitequark/master
Clifford Wolf
2019-01-15
1
-5
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+17
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manual: document some gates.
whitequark
2019-01-14
1
-9
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+11
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manual: explain $tribuf cell.
whitequark
2019-01-14
1
-0
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+10
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Merge pull request #787 from whitequark/flowmap_relax
Clifford Wolf
2019-01-15
7
-35
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+776
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flowmap: clean up terminology.
whitequark
2019-01-08
1
-17
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+18
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flowmap: implement depth relaxation.
whitequark
2019-01-08
7
-22
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+762
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Improve igloo2 example
Clifford Wolf
2019-01-08
4
-5
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+29
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Fix typo in manual
Clifford Wolf
2019-01-07
1
-1
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+1
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Bugfix in $memrd sharing
Clifford Wolf
2019-01-07
1
-2
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+6
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Merge pull request #782 from whitequark/flowmap_dfs
Clifford Wolf
2019-01-07
3
-124
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+243
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flowmap: construct a max-volume max-flow min-cut, not just any one.
whitequark
2019-01-06
1
-7
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+10
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flowmap: add -minlut option, to allow postprocessing with opt_lut.
whitequark
2019-01-04
1
-7
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+21
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flowmap: cleanup for clarity. NFCI.
whitequark
2019-01-04
3
-107
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+179
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flowmap: improve debug graph output. NFC.
whitequark
2019-01-04
1
-47
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+76
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flowmap: add link to longer version of paper. NFC.
whitequark
2019-01-04
1
-2
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+3
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Switch "bugpoint" from system() to run_command()
Clifford Wolf
2019-01-07
1
-1
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+1
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Merge pull request #783 from whitequark/bugpoint
Clifford Wolf
2019-01-07
2
-1
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+370
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bugpoint: new pass.
whitequark
2019-01-07
2
-1
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+370
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Merge pull request #780 from phire/rename_from_wire
Clifford Wolf
2019-01-06
1
-0
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+66
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Rename cells based on the wires they drive.
Scott Mansell
2019-01-06
1
-0
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+66
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Add skeleton Yosys-Libero igloo2 example project
Clifford Wolf
2019-01-05
5
-0
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+44
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Bugfix in Verilog string handling
Clifford Wolf
2019-01-05
1
-1
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+1
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Merge pull request #777 from mmicko/achronix_cell_sim_fix
Clifford Wolf
2019-01-04
1
-1
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+1
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Fix cells_sim.v for Achronix FPGA
Miodrag Milanovic
2019-01-04
1
-1
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+1
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Remove -m32 Verific eval lib build instructions
Clifford Wolf
2019-01-04
1
-29
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+0
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Merge pull request #776 from mmicko/unify_noflatten
Clifford Wolf
2019-01-04
4
-8
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+16
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Unify usage of noflatten among architectures
Miodrag Milanovic
2019-01-04
4
-8
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+16
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Update Verific default path
Clifford Wolf
2019-01-04
1
-1
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+1
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Merge pull request #775 from whitequark/opt_flowmap
Clifford Wolf
2019-01-03
3
-1
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+875
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