| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 |
| * | Update ABCREV for upstream bugfix | Eddie Hung | 2019-12-03 | 1 | -1/+1 |
| * | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 |
| * | Add INIT value to abc9_control | Eddie Hung | 2019-12-02 | 1 | -8/+8 |
| * | Cleanup | Eddie Hung | 2019-12-01 | 1 | -3/+2 |
| * | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-01 | 1 | -1/+1 |
| * | Use pool<> not std::set<> for determinism | Eddie Hung | 2019-12-01 | 1 | -4/+4 |
| * | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 |
| * | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
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| | * | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
| * | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+31 |
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| | * | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
| | * | Add multiple driver testcase | Eddie Hung | 2019-11-27 | 1 | -0/+31 |
| * | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
| * | | Add comment, use sigmap | Eddie Hung | 2019-11-27 | 1 | -2/+2 |
| * | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 5 | -7/+100 |
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| | * \ | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 2 | -3/+72 |
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| | | * | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
| | | * | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 |
| | | * | | Check for either sign or zero extension for postAdd packing | Eddie Hung | 2019-11-26 | 1 | -3/+3 |
| | | * | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 |
| | * | | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 |
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| | | * | | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 |
| | * | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 2 | -4/+24 |
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| | | * | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 2 | -4/+24 |
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| | * | | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve | Eddie Hung | 2019-11-27 | 2 | -22/+5 |
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| * | | | | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 |
| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| | * | | | | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
| * | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 4 | -34/+30 |
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| | * | | | | latch -> box | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
| | * | | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 |
| | * | | | | Fold loop | Eddie Hung | 2019-11-26 | 1 | -6/+3 |
| | * | | | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
| | * | | | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 |
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| | * | | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 |
| * | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-27 | 0 | -0/+0 |
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| | * | | | | clkpart to analyse async flops too | Eddie Hung | 2019-11-25 | 1 | -0/+8 |
| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 2 | -49/+94 |
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| | * | | | | Cleanup | Eddie Hung | 2019-11-27 | 1 | -5/+3 |
| | * | | | | Check for nullptr | Eddie Hung | 2019-11-27 | 1 | -1/+1 |
| | * | | | | Stray log_dump | Eddie Hung | 2019-11-27 | 1 | -1/+0 |
| | * | | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 2 | -42/+76 |
| | * | | | | Promote output wires in sigmap so that can be detected | Eddie Hung | 2019-11-26 | 1 | -8/+4 |
| | * | | | | Fix wire width | Eddie Hung | 2019-11-26 | 1 | -2/+2 |
| | * | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
| | * | | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -11/+25 |
| | * | | | | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 |
| | * | | | | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 |
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