aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* Merge pull request #1755 from boqwxp/add_cmd_cleanupN. Engelhardt2020-03-101-20/+17
|\
| * Clean up passes/cmds/add.cc code style.Alberto Gonzalez2020-03-101-20/+17
|/
* Merge pull request #1747 from YosysHQ/claire/partselfixEddie Hung2020-03-092-4/+10
|\
| * Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-082-4/+10
* | Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
|\ \ | |/ |/|
| * remove unused parametersN. Engelhardt2020-03-061-3/+0
| * ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
* | Merge pull request #1742 from nakengelhardt/rpc-test-againMiodrag Milanović2020-03-061-1/+2
|\ \
| * | rpc test: make frontend listen before launching yosys & introduce safeguard i...N. Engelhardt2020-03-061-1/+2
|/ /
* | Merge pull request #1739 from YosysHQ/eddie/issue1738Eddie Hung2020-03-052-7/+18
|\ \
| * | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
| * | tests: extend tests/arch/run-tests.sh for definesEddie Hung2020-03-051-3/+14
|/ /
* | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
* | Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1Eddie Hung2020-03-044-109/+244
|\ \
| * | xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
| * | xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
| * | xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
| * | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
* | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-032-6/+39
|\ \ \
| * | | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-282-6/+39
* | | | Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
* | | | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-0311-305/+388
|\ \ \ \
| * | | | Change attribute search value to specify precise location instead of simple l...Alberto Gonzalez2020-02-241-2/+2
| * | | | Change attribute search value to specify precise location instead of simple l...Alberto Gonzalez2020-02-241-2/+2
| * | | | Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-239-301/+384
* | | | | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
|\ \ \ \ \
| * | | | | verilog: instead of modifying localparam size, extend init constant exprEddie Hung2020-02-051-15/+13
* | | | | | Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-032-37/+223
|\ \ \ \ \ \ | |_|_|_|/ / |/| | | | |
| * | | | | Merge branch 'master' into eddie/submod_poEddie Hung2020-02-01219-5980/+12044
| |\ \ \ \ \
| * | | | | | Add a quick testcase for unknown modules as inoutEddie Hung2019-12-091-2/+24
| * | | | | | Use pool instead of std::set for determinismEddie Hung2019-12-021-1/+1
* | | | | | | iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-022-16/+75
* | | | | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-0243-1697/+3425
|\ \ \ \ \ \ \
| * | | | | | | Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
| * | | | | | | Small fixesEddie Hung2020-02-272-8/+8
| * | | | | | | Fixes for older compilersEddie Hung2020-02-272-2/+9
| * | | | | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
| * | | | | | | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-272-12/+20
| * | | | | | | abc9_ops: suppress -prep_box warning for abc9_flopEddie Hung2020-02-271-1/+1
| * | | | | | | xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
| * | | | | | | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
| * | | | | | | xilinx: add delays to INVEddie Hung2020-02-271-0/+3
| * | | | | | | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-273-8/+9
| * | | | | | | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-272-12/+23
| * | | | | | | Fix spacingEddie Hung2020-02-272-68/+68
| * | | | | | | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
| * | | | | | | Cleanup testsEddie Hung2020-02-272-1/+1
| * | | | | | | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
| * | | | | | | Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
| * | | | | | | abc9_ops: still emit delay table even box has no timingEddie Hung2020-02-271-3/+1
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-16 05:37:34 +0000