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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:29:53 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:29:53 -0800 |
| commit | 0f4c1906bb82f03f77683b71e597ed4802fe316a (patch) | |
| tree | fe1998f50b381616c5a8791b8807ab00c48bcf89 | |
| parent | 78929e8c3d399d47a36bb974eed74e53a3840402 (diff) | |
| download | yosys-0f4c1906bb82f03f77683b71e597ed4802fe316a.tar.gz yosys-0f4c1906bb82f03f77683b71e597ed4802fe316a.tar.bz2 yosys-0f4c1906bb82f03f77683b71e597ed4802fe316a.zip | |
Small fixes
| -rw-r--r-- | README.md | 12 | ||||
| -rw-r--r-- | kernel/timinginfo.h | 4 |
2 files changed, 8 insertions, 8 deletions
@@ -364,13 +364,13 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. -- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9` - that this module describes a LUT with propagation delays described using - `specify` statements. +- The module attribute ``abc9_lut`` is an integer attribute indicating to + `abc9` that this module describes a LUT with an area cost of this value, and + propagation delays described using `specify` statements. -- The module attribute ``abc9_box`` is a boolean specifying a blackbox or - whitebox definition, with propagation delays described using `specify` - statements, for use by `abc9`. +- The module attribute ``abc9_box`` is a boolean specifying a black/white-box + definition, with propagation delays described using `specify` statements, for + use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 5a6f4aa28..4b77c02e8 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -18,8 +18,8 @@ * */ -#ifndef TIMINGARCS_H -#define TIMINGARCS_H +#ifndef TIMINGINFO_H +#define TIMINGINFO_H #include "kernel/yosys.h" |