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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
| commit | 7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f (patch) | |
| tree | ab1520d1aa2b19eb44cb46611b425431567ca0b0 | |
| parent | 512596760b947a9ac9088856490970d0930dd951 (diff) | |
| download | yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.gz yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.bz2 yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.zip | |
xilinx: consider DSP48E1.ADREG
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 1 | ||||
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 5 | ||||
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 1 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
4 files changed, 8 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 81bcc8ac9..81f8a1d42 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -772,6 +772,7 @@ module DSP48E1 ( .RSTP(RSTP) ); $__ABC9_DSP48E1 #( + .ADREG(ADREG), .AREG(AREG), .BREG(BREG), .CREG(CREG), diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 333ac17c0..2d109ef8a 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -107,6 +107,7 @@ module $__ABC9_DSP48E1 ( output [47:0] P, output [47:0] PCOUT ); + parameter integer ADREG = 1; parameter integer AREG = 1; parameter integer BREG = 1; parameter integer CREG = 1; @@ -176,7 +177,7 @@ module $__ABC9_DSP48E1 ( // Identical comb delays to DSP48E1 in cells_sim.v generate - if (PREG == 0 && MREG == 0 && AREG == 0) + if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0) specify ($A *> P) = \A.P.comb (); ($A *> PCOUT) = \A.PCOUT.comb (); @@ -194,7 +195,7 @@ module $__ABC9_DSP48E1 ( ($C *> PCOUT) = \C.PCOUT.comb (); endspecify - if (PREG == 0 && MREG == 0 && DREG == 0) + if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0) specify ($D *> P) = \D.P.comb (); ($D *> PCOUT) = \D.PCOUT.comb (); diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index b8d0c4dc0..5604ceb0a 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -47,6 +47,7 @@ module $__ABC9_DSP48E1( output [47:0] P, output [47:0] PCOUT ); + parameter integer ADREG = 1; parameter integer AREG = 1; parameter integer BREG = 1; parameter integer CREG = 1; diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index b76055b84..63223afbf 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -3231,7 +3231,7 @@ module DSP48E1 ( endfunction generate - if (PREG == 0 && MREG == 0 && AREG == 0) + if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0) specify (A *> P) = \A.P.comb (); (A *> PCOUT) = \A.PCOUT.comb (); @@ -3264,7 +3264,7 @@ module DSP48E1 ( $setup(C, negedge CLK &&& IS_CLK_INVERTED, \C.required () ); endspecify - if (PREG == 0 && MREG == 0 && DREG == 0) + if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0) specify (D *> P) = \D.P.comb (); (D *> PCOUT) = \D.PCOUT.comb (); @@ -3286,7 +3286,7 @@ module DSP48E1 ( $setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025); endspecify - if (PREG || AREG || BREG || CREG || DREG || MREG) + if (PREG || AREG || ADREG || BREG || CREG || DREG || MREG) specify if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ; if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ; |