| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | ecp5: Increase threshold for ALU mapping | David Shah | 2019-01-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | Merge pull request #827 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-28 | 4 | -11/+21 | |
| | |\ \ \ \ | | |_|/ / | |/| | | | Fix FIRRTL to Verilog process instance subfield assignment. | |||||
| | | * | | | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 4 | -11/+21 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | |||||
| | * | | | | Fix pmgen for out-of-tree build | Clifford Wolf | 2019-02-28 | 2 | -4/+6 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | Merge pull request #833 from YosysHQ/clifford/fix831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 | |
| | |\ \ \ \ | | | | | | | | | | | | | Fix smt2 code generation for partially initialized memory words, fixe… | |||||
| | | * | | | | Fix smt2 code generation for partially initialized memowy words, fixes #831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 | |
| | |/ / / / | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | Merge pull request #832 from YosysHQ/supercover | Clifford Wolf | 2019-02-28 | 2 | -0/+93 | |
| | |\ \ \ \ | | |_|_|/ | |/| | | | Add "supercover" pass | |||||
| | | * | | | Improvements in "supercover" pass | Clifford Wolf | 2019-02-27 | 1 | -2/+18 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | Add "supercover" skeleton | Clifford Wolf | 2019-02-27 | 2 | -0/+77 | |
| | |/ / / | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module | Larry Doolittle | 2019-02-26 | 1 | -22/+22 | |
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| | * | | | Clean up some whitepsace outliers | Larry Doolittle | 2019-02-26 | 3 | -6/+6 | |
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| * | | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 2 | -4/+16 | |
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| * | | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
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| * | | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
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| * | | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
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| * | | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 | |
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| * | | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
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| * | | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
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| * | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
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| * | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
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| * | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
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| * | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
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| * | | Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant ↵ | Clifford Wolf | 2019-02-24 | 1 | -5/+1 | |
| | | | | | | | | | | | | | to -check Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #812 from ucb-bar/arrayhierarchyfixes | Clifford Wolf | 2019-02-24 | 3 | -11/+108 | |
| |\ \ | | | | | | | Define basic_cell_type() function and use it to derive the cell type … | |||||
| | * | | Address requested changes - don't require non-$ name. | Jim Lawson | 2019-02-22 | 3 | -11/+14 | |
| | | | | | | | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types. | |||||
| | * | | Fix normal (non-array) hierarchy -auto-top. | Jim Lawson | 2019-02-19 | 3 | -10/+74 | |
| | | | | | | | | | | | | | Add simple test. | |||||
| | * | | Define basic_cell_type() function and use it to derive the cell type for ↵ | Jim Lawson | 2019-02-15 | 1 | -10/+40 | |
| | | | | | | | | | | | | | array references (instead of duplicating the code). | |||||
| * | | | Cleanups in ARST handling in wreduce | Clifford Wolf | 2019-02-24 | 1 | -10/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Merge pull request #824 from litghost/fix_reduce_on_ff | Clifford Wolf | 2019-02-24 | 3 | -0/+37 | |
| |\ \ \ | | | | | | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | |||||
| | * | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | Keith Rothman | 2019-02-22 | 3 | -0/+37 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | | | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 2 | -0/+6 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Check if Verific was built with DB_PRESERVE_INITIAL_VALUE | Clifford Wolf | 2019-02-24 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Merge pull request #819 from YosysHQ/clifford/optd | Clifford Wolf | 2019-02-22 | 1 | -2/+16 | |
| |\ \ \ \ | | | | | | | | | | | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior | |||||
| | * | | | | Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine" | Clifford Wolf | 2019-02-21 | 1 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior | Clifford Wolf | 2019-02-21 | 1 | -2/+16 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Merge pull request #820 from YosysHQ/clifford/fix810 | Clifford Wolf | 2019-02-22 | 5 | -54/+26 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Fix #810 and fix #814 | |||||
| | * | | | | | Fix Travis | Clifford Wolf | 2019-02-22 | 3 | -42/+11 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It looks like that whole "Fixing Travis's git clone" code was just there to make the "git describe --tags" work. I simply removed both. Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 2 | -9/+12 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Fix handling of expression width in $past, fixes #810 | Clifford Wolf | 2019-02-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Fix segfault in printing of some internal error messages | Clifford Wolf | 2019-02-21 | 1 | -2/+2 | |
| | |/ / / / | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Merge pull request #740 from daveshah1/improve_dress | Clifford Wolf | 2019-02-22 | 3 | -34/+65 | |
| |\ \ \ \ \ | |_|/ / / |/| | | | | Improve ABC netname preservation | |||||
| | * | | | | ecp5: Use abc -dress | David Shah | 2019-02-06 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | * | | | | abc: Improved recovered netnames, also preserve src on nets with dress | David Shah | 2019-02-06 | 1 | -4/+13 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | * | | | | ice40: Use abc -dress in synth_ice40 | David Shah | 2019-02-06 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | * | | | | abc: Preserve naming through ABC using 'dress' command | David Shah | 2019-02-06 | 1 | -29/+51 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | Hotfix for 4c82ddf | Clifford Wolf | 2019-02-21 | 1 | -11/+2 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Merge pull request #822 from litghost/expand_setundef | Clifford Wolf | 2019-02-21 | 1 | -0/+29 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Add -params mode to force undef parameters in selected cells. | |||||
| | * | | | | | Add -params mode to force undef parameters in selected cells. | Keith Rothman | 2019-02-21 | 1 | -0/+29 | |
| |/ / / / / | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | | | | Merge pull request #818 from YosysHQ/clifford/dffsrfix | Clifford Wolf | 2019-02-21 | 1 | -6/+7 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 | |||||
| | * | | | | | Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 | Clifford Wolf | 2019-02-21 | 1 | -6/+7 | |
| | | |/ / / | |/| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
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